External Bus Interface (EBI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
29-20
Freescale Semiconductor
Preliminary
29.4.1.10 Configurable Bus Speed Clock Modes
The EBI supports configurable bus speed clock modes. Refer to
Section 29.1.3.4, “Configurable Bus
,” for more details on this feature.
29.4.1.11 Stop and Module Disable Modes for Power Savings
Section 29.1.3, “Modes of Operation
,” for a description of the power saving modes.
29.4.1.12 Optional Automatic CLKOUT Gating
The EBI has the ability to hold the external CLKOUT pin high when the EBI’s internal master state
machine is idle and no requests are pending. The EBI outputs a signal to the pads logic in the MCU to
disable CLKOUT. This feature is disabled out of reset, and can be enabled or disabled by the ACGE bit in
the EBI_MCR.
29.4.1.13 Misaligned Access Support
The EBI has limited misaligned access support. Misaligned non-burst chip-select transfers from internal
masters are supported. The EBI aligns the accesses when it sends them out to the external bus (splitting
them into multiple aligned accesses if necessary), so that external devices are not required to support
misaligned accesses. Burst accesses (internal master) must be 32-bit aligned.
29.4.1.13.1
Misaligned Access Support (32-bit)
shows all the misaligned access cases supported by the EBI (using a 32-bit implementation),
as seen on the internal master bus. All other misaligned cases are not supported. If an unsupported
misaligned access to the EBI is attempted (such as non-chip-select or burst misaligned access), the EBI
errors the access on the internal bus and does not start the access (nor assert TEA) externally.
1
This table applies to aligned internal master transfers only. In the case of a misaligned
internal master transfer that is split into multiple aligned external transfers, not all write
enables X’d in the table will necessarily assert. See
Section 29.4.1.13, “Misaligned
.”
2
Also applies when DBM=1 for 16-bit data bus mode.
3
This case consists of two 16-bit external transactions, but for both transactions the
WE[0:1] signals are the only WE signals affected.
Table 29-11. Misalignment Cases Supported by a 32-bit EBI (internal bus)
#
1
Program Size and
byte offset
Address
[30:31]
2,3
Data Bus Byte Strobes
4
HSIZE
5
HUNALIGN
6
1
Half @0x1
01
0110
10
1
4
—
Half @0x3
(2 AHB transfers)
11
z00
0001
1000
01
7
00
1
0
8
Word @0x1
(2 AHB transfers)
01
0111
1000
10
00
1
0
