FlexRay Communication Controller (FLEXRAY)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
30-12
Freescale Semiconductor
Preliminary
30.5.2.1
Register Reset
All registers except the
Message Buffer Cycle Counter Filter Registers (MBCCFRn)
Message Buffer Index Registers (MBIDXRn)
value on system reset. The registers mentioned above are located in physical memory blocks and, thus,
they are not affected by reset. For some register fields, additional reset conditions exist. These additional
reset conditions are mentioned in the detailed description of the register. The additional reset conditions
are explained in
30.5.2.2
Register Write Access
This section describes the write access restriction terms that apply to all registers.
30.5.2.2.1
Register Write Access Restriction
For each register bit and register field, the write access conditions are specified in the detailed register
description. A description of the write access conditions is given in
bit or field, none of the given write access conditions is fulfilled, any write attempt to this register bit or
field is ignored without any notification. The values of the bits or fields are not changed. The condition
term [A or B] indicates that the register or field can be written to if at least one of the conditions is fulfilled.
30.5.2.2.2
Register Write Access Requirements
For some of the registers, a 16-bit wide write access is required to ensure correct operation. This write
access requirement is stated in the detailed register description for each register affected
30.5.2.2.3
Internal Register Access
The following memory-mapped registers are used to access multiple internal registers.
Table 30-5. Additional Register Reset Conditions
Condition
Description
Protocol RUN Command
The register field is reset when the application writes to RUN command “0101” to the
POCCMD field in the
Protocol Operation Control Register (POCR)
.
Message Buffer Disable
The register field is reset when the application has disabled the message buffer.
This happens when the application writes 1 to the message buffer disable trigger bit
MBCCSRn.EDT while the message buffer is enabled (MBCCSn.EDS = 1) and the FlexRay
block grants the disable to the application by clearing the MBCCSRn.EDS bit.
Table 30-6. Register Write Access Restrictions
Condition
Indication
Description
Any Time
—
No write access restriction.
Disabled Mode
MCR.MEN = 0
Write access only when the FlexRay block is in Disabled Mode.
Normal Mode
MCR.MEN = 1
Write access only when the FlexRay block is in Normal Mode.
POC:config
PSR0.PROTSTATE =
POC:config
Write access only when the Protocol is in the
POC:config
state.
MB_DIS
MBCCSRn.EDS = 0
Write access only when the related Message Buffer is disabled.
MB_LCK
MBCCSRn.LCKS = 1
Write access only when the related Message Buffer is locked.
