System Interface Unit (SIU)
MPC5553/MPC5554 Microcontroller Reference Manual,
Rev. 5
Freescale Semiconductor
6-109
deserialized output signal, or the DSPI D[2] deserialized output signal. The remaining IRQ inputs are
multiplexed in the same manner. The inputs to the IRQ from each DSPI module are offset by one so that
if more than one DSPI module is connected to the same external device type, a separate interrupt can be
generated for each device. This also applies to DSPI modules connected to external devices of different
type that have status bits in the same bit location of the deserialized information.
Figure 6-144. DSPI Serialized Input Multiplexing
6.4.5.3
Multiplexed Inputs for DSPI Multiple Transfer Operation
Each DSPI module can be combined in a serial or parallel chain (multiple transfer operation). Serial
chaining allows SPI operation with an external device that has more bits than one DSPI module. An
example of a serial chain is shown in
. In a serial chain, one DSPI module operates as a master,
the second, third, or fourth DSPI modules operate as slaves. The data output (SOUT) of the master is
connected to the data input (SIN) of the slave. The SOUT of a slave is connected to the SIN of subsequent
slaves until the last module in the chain, where the SOUT is connected to an external pin, which connects
to the input of an external SPI device. The slave DSPI and external SPI device use the master peripheral
chip select (PCS) and clock (SCK). The trigger input of the master allows a slave DSPI to trigger a transfer
when a data change occurs in the slave DSPI and the slave DSPI is operating in change in data mode. The
trigger input of the master is connected to MTRIG output of the slave. If more than two DSPIs are chained
in change in data mode, a chain must be connected of MTRIG outputs to trigger inputs through the slaves
with the last slave MTRIG output connected to the master trigger input.
Parallel chaining allows the PCS and SCK from one DSPI to be used by more than one external SPI device,
thus reducing pin use of the MPC5553/MPC5554 MCU. An example of a parallel chain is shown in
. In this example, the SOUT and SIN of the two DSPIs connect to separate external SPI
devices, which share a common PCS and SCK.
To support multiple transfer operation of the DSPIs, an input multiplexor is required for the SIN, SS, SCK
IN, and trigger signals of each DSPI. The input source for the SIN input of a DSPI can be a pin or the
SOUT of any of the other three DSPIs. The input source for the SS input of a DSPI can be a pin or the
PCS0 of any of the other three DSPIs. The input source for the SCK input of a DSPI can be a pin or the
SCK output of any of the other three DSPIs. The input source for the trigger input can be the PCSS output
of any of the other three DSPIs. The input source for each DSPI SIN, SS, SCK, and trigger signal is
individually specified in the DSPI input select register (SIU_DISR).
IRQ[0]
IRQ_GPIO[203]
DSPIB[0] serialized input
DSPIC[1] serialized input
DSPID[2] serialized input
ESEL0
ESEL1
Summary of Contents for MPC5553
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