MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
11-22
Freescale Semiconductor
11.4.1.3.3
Engineering Clock (ENGCLK)
The engineering clock (ENGCLK) divider can be programmed to divide the system clock by factors from
2 to 126 in increments of two. The ENGDIV bit field in the SIU_ECCR determines the divide factor. The
reset value of ENGDIV selects an ENGCLK frequency of system clock divided by 32.
11.4.1.3.4
FlexCAN_x Clock Domains
The FlexCAN modules have two distinct software controlled clock domains. One of the clock domains is
always derived from the system clock. This clock domain includes the message buffer logic. The source
for the second clock domain can be either the system clock or a direct feed from the oscillator pin
EXTAL_EXTCLK. The logic in the second clock domain controls the CAN interface pins. The CLK_SRC
bit in the FlexCAN CTRL register selects between the system clock and the oscillator clock as the clock
source for the second domain. Selecting the oscillator as the clock source ensures very low jitter on the
CAN bus. System software can gate both clocks by writing to the MDIS bit in the FlexCAN MCR register.
shows the two clock domains in the FlexCAN modules.
Chapter 22, “FlexCAN2 Controller Area Network
” for more information on the FlexCAN modules.
11.4.1.3.5
FEC Clocks
In the MPC5553, the FEC TX_CLK and RX_CLK are inputs. An external source provides the clocks to
these pins.
11.4.2
Clock Operation
11.4.2.1
Input Clock Frequency
The FMPLL is designed to operate over an input clock frequency range as determined by the operating
mode. The operating ranges for each mode are given in
11.4.2.2
Reduced Frequency Divider (RFD)
The RFD may be used for reducing the FMPLL system clock frequency. To protect the system from
frequency overshoot during the PLL lock detect phase, the RFD must be programmed to be
1 when
changing MFD or PREDIV or when enabling frequency modulation.
11.4.2.3
Programmable Frequency Modulation
The FMPLL provides for frequency modulation of the system clock. The modulation is applied as a
triangular waveform with modulation depth and rate controlled by fields in the FMPLL_SYNCR. The
modulation depth can be set to +/-1% or +/-2% of the system frequency. The modulation rate is dependent
on the reference clock frequency.
Table 11-8. Input Clock Frequency
Mode
Symbol
Input Frequency Range
Crystal Reference
External Reference
F
ref_crystal
F
ref_ext
8 MHz –20 MHz
Bypass
F
ref_ext
0 Hz–132MHz
Dual-Controller (1:1)
F
ref_1:1
25 MHz–66 MHz
Summary of Contents for MPC5553
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