MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
11-24
Freescale Semiconductor
11.4.2.6
Loss-of-Clock Detection
The FMPLL continuously monitors the reference and feedback clocks. In the event either of the clocks fall
below a threshold frequency, the system will report a loss of clock condition. The user may enable a feature
to have the FMPLL switch the system clocks to a backup clock in the event of such a failure. Additionally,
the user may select to have the system enter reset, assert an interrupt request, or do nothing if/when the
FMPLL reports this condition.
11.4.2.6.1
Alternate/Backup Clock Selection
If the user enables loss of clock by setting FMPLL.SYNCR[LOCEN] =1, then the FMPLL will transition
system clocks to a backup clock source in the event of a clock failure as per
.
If loss of clock is enabled and the reference clock is the source of the failure, the FMPLL will enter
self-clock mode (SCM). The exact frequency during self-clock mode operation is indeterminate due to
process, voltage, and temperature variation but is guaranteed to be below the maximum system frequency.
If the FMPLL clocks have failed, the FMPLL will transition the system clock source to the reference clock.
The FMPLL remains in SCM until the next reset. Note that when the FMPLL is operated in SCM, writes
to FMPLL_SYNCR[RFD] have no effect on clock frequency. The SCM system frequency stated in the
MPC5553 Microcontroller Data Sheet
and the
MPC5554 Microcontroller Data Sheet
assumes that the
RFD has been programmed to 0x0.
If loss of clock is enabled and the loss-of-clock is due to a FMPLL failure (for example, loss of feedback
clock), the FMPLL reference becomes the system clock’s source until the next reset, even if the FMPLL
regains itself and re-locks.
A special loss of clock condition occurs when both the reference and the FMPLL fail. The failures may be
simultaneous or the FMPLL may fail first. In either case, the reference clock failure takes priority and the
FMPLL attempts to operate in SCM. If successful, the FMPLL remains in SCM until the next reset. During
SCM, modulation is always disabled. If the FMPLL cannot operate in SCM, the system remains static until
the next reset. Both the reference and the FMPLL must be functioning properly to exit reset.
11.4.2.6.2
Loss-of-Clock Reset
When a loss of clock condition is recognized, reset is asserted if the FMPLL_SYNCR[LOCRE] bit is set.
The LOCF and LOC bits in FMPLL_SYNSR are cleared after reset, therefore, the SIU_RSR must be read
to determine that a loss of clock condition occurred. LOCRE has no effect in bypass mode.
To exit reset in FMPLL mode, the reference must be present and the FMPLL must acquire lock.
Table 11-9. Loss of Clock Summary
Clock Mode
System Clock
Source before
Failure
REFERENCE FAILURE
Alternate Clock Selected by LOC
Circuitry until Reset
PLL FAILURE
Alternate Clock Selected by LOC
Circuitry until Reset
Crystal Reference
External Reference
PLL
PLL Self-Clocked Mode
PLL reference
Bypass External
Clock(s)
None
NA
Summary of Contents for MPC5553
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