MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
12-22
Freescale Semiconductor
A match on a valid calibration chip select register overrides a match on any non-calibration chip select
register, with CAL_CS0 having the highest priority. Thus the full priority of the chip selects is:
CAL_CS0....CAL_CS3, CS0....CS3.
When a match is found on one of the chip select banks, all its attributes (from the appropriate base and
option registers) are selected for the functional operation of the external memory access, such as:
•
Number of wait states for a single memory access, and for any beat in a burst access
•
Burst enable
•
Port size for the external accessed device
See
Section 12.3.1.6, “EBI Base Registers 0–3 (EBI_BRn) and EBI Calibration Base Registers 0–3
Section 12.3.1.7, “EBI Option Registers 0–3 (EBI_ORn) and EBI Calibration
Option Registers 0-3 (EBI_CAL_ORn)
,” for a full description of all chip select attributes.
When no match is found on any of the chip select banks, the default transfer attributes shown in
are used.
12.4.1.6
Burst Support (Wrapped Only)
The EBI supports burst read accesses of external burstable memory. To enable bursts to a particular
memory region, clear the BI (Burst Inhibit) bit in the appropriate base register. External burst lengths of 4
and 8 words are supported. Burst length is configured for each chip select by using the BL bit in the
appropriate base register. See
Section 12.4.2.5, “Burst Transfer
” for more details.
In 16-bit data bus mode (EBI_MCR[DBM]=1), a special 2-beat burst case is supported for reads and writes
for 32-bit non-chip select accesses only. This is to allow 32-bit coherent accesses to another MCU. See
Section 12.4.2.11, “Non-Chip-Select Burst in 16-bit Data Bus Mode
”.
Bursting of accesses that are not controlled by the chip selects is not supported for any other case besides
the special case of 32-bit accesses in 16-bit data bus mode.
Burst writes are not supported for any other case besides the special case of 32-bit non-chip select writes
in 16-bit data bus mode. Internal requests to write more than 32 bits (such as a cache line) externally are
broken up into separate 32-bit or 16-bit external transactions according to the port size. See
Section 12.4.2.6, “Small Accesses (Small Port Size and Short Burst Length)
” for more detail on these
cases.
Table 12-12. Default Attributes for Non-Chip Select Transfers
CS Attribute
Default Value
Comment
PS
0
32-bit port size
BL
0
Burst length is don’t care because burst is disabled
WEBS
0
Write enables
TBDIP
0
Don’t care because burst is disabled
BI
1
Burst inhibited
SCY
0
Don’t care because external TA is used
BSCY
0
Don’t care because external TA is used
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