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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5

Freescale Semiconductor

20-37

transfer. The TXNXTPTR field is incremented every time SPI data is transferred from the TX FIFO to the
shift register.

20.4.3.4.1

Filling the TX FIFO

Host software or the eDMA controller can add (push) entries to the TX FIFO by writing to the
DSPI

_PUSHR. When the TX FIFO is not full, the TX FIFO fill flag (TFFF) in the DSPI

_SR is set. The

TFFF bit is cleared when the TX FIFO is full and the eDMA controller indicates that a write to
DSPI

_PUSHR is complete or alternatively by host software writing a 1 to the TFFF in the DSPI

_SR.

The TFFF can generate a DMA request or an interrupt request. See

Section 20.4.9.2, “Transmit FIFO Fill

Interrupt or DMA Request (TFFF)

,” for details.

The DSPI ignores attempts to push data to a full TX FIFO; that is, the state of the TX FIFO is unchanged.
No error condition is indicated.

20.4.3.4.2

Draining the TX FIFO

The TX FIFO entries are removed (drained) by shifting SPI data out through the shift register. Entries are
transferred from the TX FIFO to the shift register and shifted out as long as there are valid entries in the
TX FIFO. Every time an entry is transferred from the TX FIFO to the shift register, the TX FIFO counter
is decremented by one. At the end of a transfer, the TCF bit in the DSPI

_SR is set to indicate the

completion of a transfer. The TX FIFO is flushed by writing a 1 to the CLR_TXF bit in DSPI

_MCR.

If an external SPI bus master initiates a transfer with a DSPI slave while the slave’s DSPI TX FIFO is
empty, the transmit FIFO underflow flag (TFUF) in the slave’s DSPI

_SR is set. See

Section 20.4.9.4,

“Transmit FIFO Underflow Interrupt Request (TFUF)

,”for details.

20.4.3.5

Receive First In First Out (RX FIFO) Buffering Mechanism

The RX FIFO functions as a buffer for data received on the SIN pin. The RX FIFO holds four received
SPI data frames. SPI data is added to the RX FIFO at the completion of a transfer when the received data
in the shift register is transferred into the RX FIFO. SPI data is removed (popped) from the RX FIFO by
reading the DSPI

_POPR register. RX FIFO entries can only be removed from the RX FIFO by reading

the DSPI

_POPR or by flushing the RX FIFO. For more information on the DSPI

_POPR, refer to

Section 20.3.2.7, “DSPI POP RX FIFO Register (DSPIx_POPR)

.”

The RX FIFO counter field (RXCTR) in the DSPI status register (DSPI

_SR) indicates the number of

valid entries in the RX FIFO. The RXCTR is updated every time the DSPI _POPR is read or SPI data is
copied from the shift register to the RX FIFO.

The POPNXTPTR field in the DSPI

_SR points to the RX FIFO entry that is returned when the

DSPI

_POPR is read. The POPNXTPTR contains the positive, 32-bit word offset from DSPI

_RXFR0.

For example, POPNXTPTR equal to two means that the DSPI

_RXFR2 contains the received SPI data

that will be returned when DSPI

_POPR is read. The POPNXTPTR field is incremented every time the

DSPI

_POPR is read. POPNXTPTR rolls over every four frames on the MPC5553/MPC5554.

20.4.3.5.1

Filling the RX FIFO

The RX FIFO is filled with the received SPI data from the shift register. While the RX FIFO is not full,
SPI frames from the shift register are transferred to the RX FIFO. Every time an SPI frame is transferred
to the RX FIFO the RX FIFO counter is incremented by one.

Freescale Semiconductor MPC5553, Reference Manual

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