MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
21-30
Freescale Semiconductor
For a 9-bit data character, data sampling of the stop bit takes the receiver 170 RT cycles, as shown below:
With the misaligned character shown in
, the receiver counts 170 RT cycles at the point when
the count of the transmitting device is 11 bit times x 16 RT cycles = 176 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit
character with no errors is 3.40%, as is shown below:
21.4.5.6
Receiver Wake-up
The receiver can be put into a standby state, which enables the eSCI to ignore transmissions intended only
for other receivers in multiple-receiver systems. Setting the receiver wake-up bit, ESCI
x
_CR1[RWU], in
eSCI control register 1 (ESCI
x
_CR1) puts the receiver into standby state during which receiver interrupts
are disabled. The eSCI will still load the received data into the ESCI
x
_DR, but it will not set the receive
data register full, RDRF, flag.
The transmitting device can address messages to selected receivers by including addressing information
(address bits) in the initial frame or frames of each message. See section
,”
for an example of address bits.
The WAKE bit in eSCI control register 1 (ESCI
x
_CR1) determines how the eSCI is brought out of the
standby state to process an incoming message. The WAKE bit enables either idle line wake-up or address
mark wake-up.
21.4.5.6.1
Idle Input Line Wake-up (WAKE = 0)
Using the receiver idle input line wake-up method allows an idle condition on the RXD signal clears the
ESCI
x
_CR1[RWU] bit and wakes up the eSCI. The initial frame or frames of every message contain
addressing information. All receivers evaluate the addressing information, and receivers for which the
message is addressed process the frames that follow. Any receiver for which a message is not addressed
can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on
standby until another idle character appears on the RXD signal.
Idle line wake-up requires that messages be separated by at least one idle character and that no message
contains idle characters.
The idle character that wakes a receiver does not set the receiver idle bit, ESCI
x
_SR[IDLE], or the receive
data register full flag, RDRF.
The idle line type bit, ESCI
x
_CR1[ILT], determines whether the receiver begins counting logic 1s as idle
character bits after the start bit or after the stop bit.
21.4.5.6.2
Address Mark Wake-up (WAKE = 1)
Using the address mark wake-up method allows a logic 1 in the most significant bit (msb) position of a
frame to clear the RWU bit and wake-up the eSCI. The logic 1 in the msb position marks a frame as an
address frame that contains addressing information. All receivers evaluate the addressing information, and
the receivers for which the message is addressed process the frames that follow. Any receiver for which a
10 bit times
16 RT cycles
10 RT cycles
+
170 RT cycles
=
176 – 170
176
--------------------------
100
3.40%
=
Summary of Contents for MPC5553
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