MPC562/MPC564 Compression Features
MPC561/MPC563 Reference Manual, Rev. 1.2
A-18
Freescale Semiconductor
A.4
Decompressor Class Configuration Registers (DCCR0-15)
The DCCR fields are programmed to achieve maximum flexibility in the vocabulary tables placement into
the two DECRAM banks under constraints, implied by hardware, which are:
•
A bypass field must always be in the second field of the compressed instruction
28
IFM
Ignore first match, only for I-bus
breakpoints
0 = Do not ignore first match,
used for “go to x” (reset
value)
1 = Ignore first match (used
for “continue”)
0 = Do not ignore first match,
used for “go to x” (reset
value)
1 = Ignore first match (used
for “continue”)
29:31
ISCT_SER
RCPU serialize control and
Instruction fetch show cycle
These bits control
serialization and instruction
fetch show cycles. See
for the bit
definitions.
NOTE: Changing the
instruction show cycle
programming starts to take
effect only from the second
instruction after the actual
mtspr
to ICTRL.
These bits control
serialization and instruction
fetch show cycles. See
for the bit
definitions.
NOTE: Changing the
instruction show cycle
programming starts to take
effect only from the second
instruction after the actual
mtspr
to ICTRL.
1
MPC562/MPC564 only.
Table A-2. ISCT_SER Bit Descriptions
Serialize
Control
(SER)
Instruction
Fetch
(ISCTL)
Functions Selected
0
00
RCPU is fully serialized and show cycles will be performed for all fetched instructions (reset
value)
0
01
RCPU is fully serialized and show cycles will be performed for all changes in the program flow
0
10
RCPU is fully serialized and show cycles will be performed for all indirect changes in the
program flow
0
11
RCPU is fully serialized and no show cycles will be performed for fetched instructions
1
00
Illegal. This mode should not be selected.
1
01
RCPU is not serialized (normal mode) and show cycles will be performed for all changes in
the program flow
1
10
RCPU is not serialized (normal mode) and show cycles will be performed for all indirect
changes in the program flow
1
11
RCPU is not serialized (normal mode) and no show cycles will be performed for fetched
instructions
Table A-1. ICTRL Bit Descriptions (continued)
Bits
Mnemonic
Description
Function
Non-compressed mode
Compressed Mode
1
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
