Memory Controller
MPC561/MPC563 Reference Manual, Rev. 1.2
10-6
Freescale Semiconductor
For addition details, refer to
Section 9.5.4, “Burst Transfer
."
10.2.6
Reduced Data Setup Time
In order to meet timing requirements when interfacing to external memories, the data setup time can be
reduced. This mode can be selected by programming the BR
x
registers. Thus there is flexibility in how
each region can be configured to operate. The operation mode will be determined dynamically according
to a particular access type. This means that for a memory region with the reduced setup time mode enabled,
the mode will automatically switch to disabled when there is no requirement for the reduced setup time,
(e.g., a back-to-back load/store access). For a new access with burst length more than 1, the operation
mode will be automatically switched back to the reduced setup time mode.
Reduced setup time can be selected via the SST bit in BR[0
:
3]. See
Section 10.9.3, “Memory Controller
” for more details. If SCCR[EBDF] is greater than 0, however, an external burst
access with reduced data setup time will corrupt a load/store to any USIU register.
The reduced setup time mode may or may not have a performance impact, depending on the properties of
the memory. Namely, there is always an additional empty cycle between two burst sequences. On the other
hand, this additional cycle, under certain conditions, may be compensated for by reducing the number of
cycles in initial data access and sequential burst beats.
10.2.6.1
Case 1: Normal Setup Time
Initial access:
To derive the number of clocks required, divide by the system clock cycle time:
therefore 4 cycles are required
Burst access:
The number of clocks required
therefore 2 clocks are required.
This case is illustrated in
Table 10-1. Timing Requirements for Reduced Setup Time
CPU Specification
Memory Device Requirements
Cycle time at 56 MHz = 17.9 ns
Initial access time = 49 ns
Short setup time = 3 ns
Burst access time = 13 ns
Normal setup time = 6 ns
Additional delay arising from on-board wires and clock skew between
internal clock and CLKOUT
Initial access time of memory
Data setup time of CPU
Delays
+
+
49
6
1
56ns
=
+
+
=
56
17.9
----------
3.13
=
Burst access time of memory
Data setup time of CPU
Delays
13
6
1
20ns
=
+
+
=
+
+
20
17.9
----------
=
1.11
=
Summary of Contents for MPC561
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Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
