QADC64E Legacy Mode Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-33
or write the result word table, but in normal operation, the software reads the result word table to obtain
analog conversions from the QADC64E. Unimplemented bits are read as zeros, and write operations do
not have any effect. See
for a diagram of the result word table
While there is only one result word table, the data can be accessed in three different data formats:
•
Right justified in the 16-bit word, with zeros in the higher order unused bits
•
Left justified, with the most significant bit inverted to form a sign bit, and zeros in the unused lower
order bits
•
Left justified, with zeros in the lower order unused bits
The left justified, signed format corresponds to a half-scale, offset binary, two’s complement data format.
The data is routed onto the IMB3 according to the selected format. The address used to access the table
determines the data alignment format. All write operations to the result word table are right justified.
The three result data formats are produced by routing the RAM bits onto the data bus. The software
chooses among the three formats by reading the result at the memory address which produces the desired
data alignment.
The result word table is read/write accessible by software. During normal operation, application software
only needs to read the result table. Write operations to the table may occur during test or debug breakpoint
operation. When locations in the CCW table are not used by an application, software could use the
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LSB
15
Field
—
RESULT
SRESET
0000_00
Undefined
Addr
0x30 4A80–4AFF (RJURR_A); 0x30 4E80–4EFF (RJURR_B)
Figure 13-17. Right Justified, Unsigned Result Format (RJURR)
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LSB
15
Field
S
1
1
S = Sign bit.
RESULT
—
SRESET
Undefined
00_0000
Addr
0x30 4B00–4B7F (LJSRR_A); 0x30 4F00–4F7F (LJSRR_B)
Figure 13-18. Left Justified, Signed Result Format (LJSRR)
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LSB
15
Field
RESULT
—
SRESET
Undefined
00_0000
Addr
0x30 4B80–4BFF (LJURR_A); 0x30 4F80–4FFF (LJURR_B)
Figure 13-19. Left Justified, Unsigned Result Register (LJURR)
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
