Modular Input/Output Subsystem (MIOS14)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-25
Table 17-12. MMCSMSCR Bit Descriptions
Bits
Name
Description
0
PINC
Clock input signal status bit — This read-only status bit reflects the logic state of the clock input
signal MMCnC (MDA11, MDA13, MDA27, MDA30, PWM16, and PWM18).
1
PINL
Modulus load input signal status bit — This read-only status bit reflects the logic state of the
modulus load signal MMCnL (MDA12, MDA14, MDA28, MDA31, PWM17, and PWM19).
2
FREN
Freeze enable — This active high read/write control bit enables the MMCSM to recognize the
MIOB freeze signal.
3
EDGN
Modulus load falling-edge sensitivity — This active high read/write control bit sets falling-edge
sensitivity for the MMCnL signal, such that a high-to-low transition causes a load of the
MMCSMCNT.
4
EDGP
Modulus load rising-edge sensitivity
This active high read/write control bit sets rising-edge sensitivity for the MMCnL signal, such that
a low-to-high transition causes a load of the MMCSMCNT.
See
for details about edge sensitivity.
5:6
CLS
Clock select — These read/write control bits select the clock source for the modulus counter.
Either the rising edge or falling edge of the clock signal on the MMCnC signal may be selected,
as well as, the internal MMCSM prescaler output or disable mode (no clock source). See
for details about the clock selection.
7
—
Reserved
8:15
CP
Clock prescaler — This 8-bit data field is also accessible as an 8-bit data register. It stores the
two’s complement of the modulus value to be loaded into the built-in 8-bit clock prescaler. The
new value is loaded into the prescaler counter on the next counter overflow, or upon setting the
CLS1 — CLS0 bits for selecting the clock prescaler as the clock source.
gives the clock divide ratio according to the value of CP.
Table 17-13. MMCSMCNT Edge Sensitivity
EDGN
EDGP
Edge Sensitivity
1
1
MMCSMCNT load on rising and falling edges
1
0
MMCSMCNT load on falling edges
0
1
MMCSMCNT load on rising edges
0
0
None (disabled)
Table 17-14. MMCSMCNT Clock Signal
CLS
Clocking Selected
11
MMCSM clock prescaler
10
Clock signal rising-edge
01
Clock signal falling-edge
00
None (disable)
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
