Modular Input/Output Subsystem (MIOS14)
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
17-69
17.12.5 Interrupt Control Section (ICS)
The interrupt control section delivers the interrupt level to the CPU. The interrupt control section adapts
the characteristics of the MIOB request bus to the characteristics of the interrupt structure of the IMB3.
When at least one of the flags is set on an enabled level, the ICS receives a signal from the corresponding
IRQ pending register. This signal is the result of a logical “OR” between all the bits of the IRQ pending
register.
The signal received from the IRQ pending register is associated with the interrupt level register within the
ICS. This level is coded on five bits in this register: three bits represent one of eight levels and the two
other represent the four time multiplex slots. According to this level, the ICS sets the correct IRQ[7:0] lines
with the correct ILBS[1:0] time multiplex lines on the peripheral bus. The CPU is then informed as to
which of the thirty-two interrupt levels is requested.
Based on the interrupt level requested, the software must determine which submodule requested the
interrupt. The software may use a find-first-one type of instruction to determine, in the concerned MIRSM,
which of the bits is set. The CPU can then serve the requested interrupt.
17.12.6 MBISM Interrupt Registers
shows the MBISM interrupt registers.
17.12.6.1 MIOS14 Interrupt Level Register 0 (MIOS14LVL0)
This register contains the interrupt level that applies to the submodules numbers 15 to zero.
7:9
IRP24:22
Pending Bits — MMCSM pending bits [24:22]
10:15
IRP21:16
Pending Bits — PWMSM pending bits [21:16]
Table 17-41. MBISM Interrupt Registers Address Map
Address
Register
0x30 6C30
MIOS14 Interrupt Level Register 0 (MIOS14LVL0)
See
for bit descriptions.
0x30 6C70
MIOS14 Interrupt Level Register 1 (MIOS14LVL1)
See
for bit descriptions.
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LSB
15
Field
—
LVL
TM
—
SRESET
0000_0000_0000_0000
Addr
0x30 6C30
Figure 17-41. MIOS14 Interrupt Level Register 0
(MIOS14LVL0)
Table 17-40. MIOS14RPR1 Bit Descriptions (continued)
Bits
Name
Description
Summary of Contents for MPC561
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