Programming Model
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor
26-119
If the Interrupt Status Register is written from the core processor, 1s in the value written are
recorded in the Interrupt Status Register if the corresponding bit is unmasked in the Interrupt
Mask Register. All other bits are cleared. This register can also be cleared by setting the RI bit of
the DEU Reset Control Register (see Section 26.5.7.4, DEU Reset Control Register (DEURCR),
on page 26-116). The definition of each bit in the DEU Interrupt Status Register is listed in Table
26-38.
Table 26-38. DEUISR Field Descriptions
Name
Reset
Description
Settings
—
63–14
0
Reserved. Write to zero for future compatibility.
KPE
13
0
Key Parity Error
If set, defined parity bits in the keys written to
the key registers do not reflect odd parity
correctly.
Note:
Key register 2 and key register 3 are
checked for parity only if the
appropriate DEU Mode Register bit
indicates triple DES. Also, key register
3 is checked only if key size reg = 24.
Key register 2 is checked only if key
size reg = 16 or 24.
0
No key parity error detected.
1
Key parity error.
IE
12
0
Internal Error
Indicates whether an internal processing error
was detected while the DEU was processing.
0
No internal error detected.
1
Internal error.
ERE
11
0
Early Read Error
Indicates whether the DEU IV register was read
while the DEU was performing encryption.
0
No early read error detected.
1
Early read error.
CE
10
0
Context Error
If set, indicates that DEU key register, the Key
Size Register, Data Size Register, Mode
Register, or IV register was modified while DEU
was performing encryption.
0
No context error detected.
1
Context error.
KSE
9
0
Key Size Error
IF set, indicates that an inappropriate value (8
being appropriate for single DES, and 16 and
24 being appropriate for triple DES) was written
to the DEU Key Size Register.
0
No key size error detected.
1
Key size error.
DSE
8
0
Data Size Error
If set, a value was written to the DEU Data Size
Register that is not a multiple of 64 bits.
0
No data size error detected.
1
Data size error.
ME
7
0
Mode Error
If set, an illegal value was detected in the Mode
Register.
0
No mode error detected.
1
Mode error.
AE
6
0
Address Error
If set, an illegal read or write address was
detected within the DEU address space.
0
No address error detected.
1
Address error detected.
OFE
5
0
Output FIFO Error
If set, the DEU output FIFO was detected
non-empty upon write of DEU Data Size
Register.
0
No output FIFO error detected.
1
Output FIFO error.
IFE
4
0
Input FIFO Error
If set, the DEU input FIFO was detected
non-empty upon generation of a done interrupt.
0
No input FIFO error detected.
1
Input FIFO error.
Summary of Contents for MSC8144E
Page 1: ...MSC8144E Reference Manual Quad Core Media Signal Processor MSC8144ERM Rev 3 July 2009 ...
Page 48: ...MSC8144E Reference Manual Rev 3 xlviii Freescale Semiconductor ...
Page 86: ...MSC8144E Reference Manual Rev 3 1 38 Freescale Semiconductor Overview ...
Page 168: ...MSC8144E Reference Manual Rev 3 3 60 Freescale Semiconductor External Signals ...
Page 242: ...MSC8144E Reference Manual Rev 3 5 26 Freescale Semiconductor Reset ...
Page 314: ...MSC8144E Reference Manual Rev 3 8 24 Freescale Semiconductor General Configuration Registers ...
Page 414: ...MSC8144E Reference Manual Rev 3 10 14 Freescale Semiconductor MSC8144E SC3400 DSP Subsystem ...
Page 452: ...MSC8144E Reference Manual Rev 3 11 38 Freescale Semiconductor Internal Memory Subsystem ...
Page 520: ...MSC8144E Reference Manual Rev 3 12 68 Freescale Semiconductor DDR SDRAM Memory Controller ...
Page 1070: ...MSC8144E Reference Manual Rev 3 21 28 Freescale Semiconductor Timers ...
