Enhanced Queued Analog-to-Digital Converter (EQADC)
27-78
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27.7.4.5
Hardware Trigger Event Detection
On this device, the on-chip triggers bypass the filter and the off-chip ETRIG triggers are always filtered
and subject to the minimum filter length of 2 clocks. When the filter is bypassed, the ETRIG input signal
is not filtered and the logic after the filter receives a copy of this input trigger signal.
The Digital Filter Length field in
Section 27.6.2.2, EQADC External Trigger Digital Filter Register
, specifies the minimum number of platform clocks that the ETRIG0-5 signals must be
held at a logic level to be recognized as valid. All ETRIG signals are filtered. A counter for each queue
trigger is implemented to detect a transition between logic levels. The counter counts at the platform clock
rate. The corresponding counter is cleared and restarted each time the signal transitions between logic
levels. When the corresponding counter matches the value specified by the Digital Filter Length field in
Section 27.6.2.2, EQADC External Trigger Digital Filter Register (EQADC_ETDFR)
, the EQADC
considers the ETRIG logic level to be valid and passes that new logic level to the rest of the EQADC.
The filter is only for filtering the ETRIG signal. Logic after the filter checks for transitions between filtered
values, such as for detecting the transition from a filtered logic level zero to a filter logic level one in rising
edge external trigger mode. The EQADC can detect rising edge, falling edge, or level gated external
triggers. The digital filter will always be active independently of the status of the MODE
x
field in
Section 27.6.2.5, EQADC CFIFO Control Registers (EQADC_CFCR)
, but the edge, level detection logic
is only active when MODEx is set to a value different from disabled, and in case MODEx is set to single
scan mode, when the SSS bit is asserted. Note that the time necessary for a external trigger event to result
into a CFIFO status change is not solely determined by the DFL field in the
External Trigger Digital Filter Register (EQADC_ETDFR)
. After being synchronized to the platform
clock and filtered, a trigger event is checked against the CFIFO trigger mode. Only then, after a valid
trigger event is detected, the EQADC accordingly changes the CFIFO status. Refer to
for an
example.
Figure 27-55. ETRIG Event Propagation Example
27.7.4.6
CFIFO Scan Trigger Modes
The EQADC supports two different scan modes, single-scan and continuous-scan. Refer to
for a summary of these two scan modes. When a CFIFO is triggered, the EQADC scan mode determines
whether the EQADC will stop command transfers from a CFIFO, and wait for software intervention to
Platform Clock
External Trigger Signal
Filtered External
CFIFO Status
Trigger Signal
Signal State at Input Pin
MODEx
IDLE
WAITING FOR TRIGGER
TRIGGERED
DISABLED
CONTINUOUS SCAN HIGH LEVEL GATED EXTERNAL TRIGGER
Trigger Detection Delay
Trigger Synchronization and Filtering Delay
1
)
Notes:
1. This delay is about 2 clocks when the filter bypass control is asserted.
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
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