Enhanced Queued Analog-to-Digital Converter (EQADC)
27-110
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27.7.8
EQADC DMA/Interrupt Request
lists methods to generate interrupt requests in the EQADC queuing control and triggering
control. The DMA/interrupt request select bits and the DMA/interrupt enable bits are described in
Section 27.6.2.6, EQADC Interrupt and DMA Control Registers (EQADC_IDCR)
, and the interrupt flag
bits are described in
Section 27.6.2.7, EQADC FIFO and Interrupt Status Registers (EQADC_FISR)
depicts all interrupts and DMA requests generated by the EQADC.The Result FIFO Overflow
Interrupt, the Command FIFO Underflow Interrupt, and the Command FIFO Trigger Overrun Interrupt
requests of ALL CFIFOs are ORed to generate single interrupt request from the eQADC. This combined
interrupt request is asserted whenever one of the following flags becomes asserted: RFOFx, CFUFx, and
TORFx (assuming that all interrupts are enabled).
describes a list of methods to generate DMA requests in the EQADC.
Table 27-44. EQADC FIFO Interrupt Summary
1
NOTES:
1
For details refer to
Section 27.6.2.7, EQADC FIFO and Interrupt Status Registers (EQADC_FISR)
, and
Section 27.6.2.6, EQADC Interrupt and DMA Control Registers (EQADC_IDCR)
Interrupt Condition
Clearing
Mechanism
Non Coherency
Interrupt
NCIEx = 1
NCFx = 1
Clear NCFx bit by writing a “1” to the bit.
Result FIFO Overflow
Interrupt
2
2
Apart from generating an independent interrupt request for when a RFIFO Overflow Interrupt, a CFIFO
Underflow Interrupt, and a CFIFO Trigger Overrun Interrupt occurs, the EQADC also provides a combined
interrupt request at which these requests from ALL CFIFOs are ORed. Refer to
for details.
RFOIEx = 1
RFOFx = 1
Clear RFOFx bit by writing a “1” to the bit.
Command FIFO
Underflow Interrupt
CFUIEx = 1
CFUFx = 1
Clear CFUFx bit by writing a “1” to the bit.
Result FIFO Drain
Interrupt
RFDEx = 1
RFDSx = 0
RFDFx = 1
Clear RFDFx bit by writing a “1” to the bit.
Command FIFO
Fill Interrupt
CFFEx = 1
CFFSx = 0
CFFFx = 1
Clear CFFFx bit by writing a “1” to the bit.
End of Queue Interrupt
EOQIEx = 1
EOQFx = 1
Clear EOQFx bit by writing a “1” to the bit.
Pause Interrupt
PIEx = 1
PFx =1
Clear PFx bit by writing a “1” to the bit.
Trigger Overrun
Interrupt
TORIEx = 1
TORFx =1
Clear TORFx bit by writing a “1” to the bit.
Table 27-45. EQADC FIFO DMA Summary
1
DMA Request
Condition
Clearing Mechanism
Result FIFO Drain
DMA Request
RFDEx = 1
RFDSx = 1
RFDFx = 1
The EQADC automatically clears the RFDFx when RFIFOx
becomes empty. Writing “1” to the RFDFx bit is not allowed.
Command FIFO Fill
DMA Request
CFFEx = 1
CFFSx = 1
CFFFx = 1
The EQADC automatically clears the CFFFx when CFIFOx becomes
full. Writing “1” to the CFFFx bit is not allowed.
Summary of Contents for PXR4030
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