Decimation Filter
28-30
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
Figure 28-15. Filter Configuration Paths (FIR or 1x4Poles IIR)
28.3.10 Rounding
The Decimation Filter performs rounding operations in two different locations, as shown in
:
•
to obtain the filter output result with 16 bits
•
to obtain the IIR feedback result to be stored in tap4 registers with 24 bits
The rounding mechanism implements the Convergent Rounding methodology (also known as
round-to-nearest even number), which makes the decision on rounding up or down based on the value of
the lower portion of data to be rounded (LS_WORD). The rounding up/down condition is equal to the
traditional rounding except when the LS_WORD has the format {1000...00}. In this particular case, the
rounding procedure is like the example of
. If the MS_WORD is odd, the value is rounded
up. Otherwise the value is rounded down.
By-pass
FIR
Z
-1
Z
-1
Z
-1
Z
-1
+
Coefficient 2
Tap1
Coefficient 4
Coefficient 3
Tap2
Tap3
Tap0
Coefficient 1
x(n)
+
Coefficient 6
Tap5
Coefficient 8
Coefficient 7
Tap6
Tap7
Tap4
Coefficient 5
y(n)
01
10
B
Z
-1
Z
-1
Z
-1
Z
-1
Round/Sat
FTYPE[1:0]
Round/Sat
IIR
00
A
Scale Factor S
Register
Coefficient 0
Summary of Contents for PXR4030
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