Enhanced Time Processing Unit (eTPU2)
Freescale Semiconductor
29-7
PXR40 Microcontroller Reference Manual, Rev. 1
In the Host address space each parameter occupies four bytes. eTPU usage of the upper byte is achieved
by having a 32-bit P register which can access the upper byte, the lower 24 bits or all the 32 bits. The
microcode can switch between access sizes at any time.
Each Function may require a different number of parameters. During the eTPU initialization the Host has
to program channel base addresses, allocating proper parameters for each channel according to its selected
Function.
29.1.1.1.5
Scheduler
Out of reset, all channels are disabled. The Host CPU makes a channel active by assigning it one of three
priorities: high, middle, or low. The Scheduler determines the order in which channels are serviced based
on channel number and assigned priority. The priority mechanism, implemented in hardware, ensures that
all requesting channels are serviced. For additional details refer to
.
29.1.1.1.6
Microengine
eTPU microengine executes each instruction in a microcycle of two system clocks, while prefetching the
next instruction through an instruction pipeline. Instruction execution time is constant unless it gets wait
states from the SDM arbitration. Two eTPU Engines share code memory without having any performance
degradation by interleaving their accesses (the Shared Code Memory has one-clock access time).
Instruction width is 32 bits. The microengine instruction set provides basic arithmetic and logic operations,
flow control (jumps and subroutine calls), SDM access, and Channel configuration and control. The
instruction formats are defined in such a way that allow particular combinations of two or three of these
operations with unconflicting resources to be executed in parallel in the same microcycle.
Microengine has also an independent Multiply/Divide/MAC unit that performs these complex operations
in parallel with other microengine instructions.
Channel functionality is tightly integrated to the instruction set through Channel Control operations and
conditional Branch operations, which support jumps/calls on Channel-specific conditions. This allows
quick and terse Channel configuration and control code, contributing to reduced service time.
29.1.1.1.7
Dual eTPU Engine Module
The eTPU A/B implementation includes two eTPU Engines sharing SDM and the same code in SCM.
The two eTPU Engines share the Bus Interface Unit (BIU) and the data memory (SDM) which enable
Host-eTPU and eTPU Engine-Engine communication. The shared BIU includes coherency logic which
supports dual parameter (8 bytes) coherency in transfers between Host and eTPU, using a temporary
parameter area within the SDM. More details on this can be found on
Section 29.3.4, Parameter Sharing
.
29.1.2
Features
29.1.2.1
eTPU Feature Summary
The eTPU includes these distinctive features:
Summary of Contents for PXR4030
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