External Bus Interface (EBI)
30-4
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
30.1.4.6
Multiplexed Address on Data Bus Mode
This mode covers several cases aimed at reducing pin count on MCU and external components. In this
mode, the D_ADD_DAT pins will drive (for internal master cycles) the address value on the first clock of
the cycle (while D_TS is asserted).
The memory controller supports per-chip-select selection of multiplexing address/data through the
BRx[AD_MUX] bit.
Address on Data bus multiplexing also supports the 16-bit data bus mode (MCR[DBM]=1) and 16-bit
memories (ORx[PS]=1). The user can select which 16 data signals are used (D_ADD_DAT[0:15] or
D_ADD_DAT[16:31]) by writing the D16_31 bit in the EBI_MCR. For either setting of D16_31, the 16
LSBs of external address (D_ADD[16:31]) are driven onto the selected 16 D_ADD_DAT pins. If
additional address lines are required to interface to the memory, then non-muxed address pins are
sometimes (see note below) required to complete the address space (e.g. D_ADD[8:15] are commonly
present as non-muxed address pins).
NOTE
The EBI also drives the unused 16 D_ADD_DAT signals with the MSBs of
the external address, zero-padded in front (e.g. when D16_31 bit is set for a
device with 24 D_ADD pins, the EBI drives (0b00000000, D_ADD[8:15])
on D_ADD_DAT[0:15]. This allows the device to optionally use
D_ADD_DAT[8:15] for the upper 8 external address lines instead of
requiring separate non-muxed D_ADD[8:15] pins. This is relevant
primarily for devices that support both 32-bit and 16-bit A/D muxed
operation, so therefore have D_ADD_DAT[0:31] pins present on the device,
and in that case are not required to have separate D_ADD pins.
For more details (e.g. timing diagrams), see
Section 30.4.2.12, Address Data Multiplexing
The Address Latch Enable (ALE) indicates when the address is present during a multiplexed bus access
using a D_ADD_DAT signal. This can be used in conjunction with an external latch to hold the state of
the address access if connecting the MCU to a non-multiplexed bus compatible memory. ALE signal
timing is shown in
.
Figure 30-1. ALE signal timing
fperiph
A/D
t
ALEhigh
CLKOUT
ALE
TS
ADDR
DATA
t
ALEnegatedToADDRinvalid
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
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