External Bus Interface (EBI)
Freescale Semiconductor
30-35
PXR40 Microcontroller Reference Manual, Rev. 1
30.4.2.6
Small Accesses (Small Port Size and Short Burst Length)
In this context, a
small access
refers to an access whose burst length and port size (BL, PS bits in Base
Register for chip-select access or default burst disabled, 32-bit port for non-chip-select access) are such
that the number of bytes requested by the internal master cannot all be fetched (or written) in one external
transaction. If this is the case, the EBI initiates multiple transactions until all the requested data is
transferred. It should be noted that all the transactions initiated to complete the data transfer are considered
as an atomic transaction, so the EBI does not allow other unrelated master accesses to intervene between
the transfers.
shows all the combinations of burst length, port size, and requested byte count that cause the
EBI to run multiple external transactions to fulfill the request.
In most cases, the timing for small accesses is the same as for normal single-beat and burst accesses, except
that multiple back-to-back external transfers are executed for each internal request. These transfers have
no additional dead cycles in-between that are not present for back-to-back stand-alone transfers except for
the case of writes with an internal request size of >64 bits, discussed in
Section 30.4.2.6.2, Small Access
Example #2: 32-byte Write with External D_TA
The following sections show a few examples of small accesses. The timing for the remaining cases in
can be extrapolated from these and the other timing diagrams in this document.
30.4.2.6.1
Small Access Example #1: 32-bit Write to 16-bit Port
shows an example of a 32-bit write to a 16-bit port, requiring two 16-bit external transactions.
Table 30-14. Small Access Cases
Byte Count Requested
by internal master
Burst Length
Port Size
# External Accesses to
Fulfill Request
Non-Burstable Chip-Select Banks (BI=1) or Non-Chip-Select Access
4
1 beat
16-bit
2/1
1
1
In 32-bit data bus mode (DBM=0 in EBI_MCR), two accesses are performed. In 16-bit data bus mode
(DBM=1), one 2-beat burst access is performed and this is not considered a “small access” case.
See
Section 30.4.2.9, Non-Chip-Select Burst in 16-bit Data Bus Mode
for this special DBM=1 case.
8
1 beat
32-bit
2
8
1 beat
16-bit
4
32
2
2
Only supported for case of 64-bit internal AMBA data bus.
1 beat
32-bit
8
1 beat
16-bit
16
Burstable Chip-Select Banks (BI=0)
4 words
16-bit (8 beats), 32-bit (4
beats)
2
Summary of Contents for PXR4030
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