Frequency Modulated Phase-Locked Loop (FMPLL)
6-22
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
6.5
Resets
This section describes the reset operation of the PLL, including power-on reset and normal resets. The
reset values of registers and signals are provided in other sections.
6.5.1
Clock Mode Selection
The initial clock mode is reflected in the MODE, PLLSEL, and PLLREF bits of the synthesizer status
register (SYNSR) as well as the ESYNCR1[CLKCFG[2:0]] bit field. The clock mode can be modified by
writing to the CLKCFG[2:0] bit field. The synthesizer status register then reflects the newly-selected PLL
clock mode.
summarizes clock mode selection.
6.5.1.1
Power-On Reset (POR)
The PLL will not operate until the POR state has ended. Refer to
PXR40 Microcontroller Data Sheet
for
these thresholds. At this point, the PLL operates in self-clocked mode (SCM) until a valid reference clock
is detected by the internal clock monitor circuit.
Internal to the PLL, the VCO is held in reset until the negation of the POR signal. This prevents the PLL
from attempting to lock before its supplies are within specification, which can cause VCO/loop gain to be
lower than what the analog loop is designed for.
6.5.1.2
External Reset
After POR has negated, the PLL will begin its lock detect algorithm if Normal Mode is selected. However,
if a valid reference is not present, the PLL will continue to operate in Self Clocked Mode until one is
present. PLL configuration at POR may be selected by external pins PLLCFG[0:1] or reset state values of
configuration registers.
After the initial lock with the default divider settings (assuming Normal Mode was selected), you may
write to the SYNCR/ESYNCR(s) to modify the dividers for the desired operating frequency. The PLL may
Table 6-13. Clock Mode Selection
Package Pins
1
1
The PLLCFG[2] pin configures the crystal oscillator range:
PLLCFG[2] = 0, for 8 MHz to 20 MHz
PLLCFG[2] = 1, for 40 MHz
Clock Mode
Synthesizer Status Register (SYNSR)
MODE, PLLSEL, and PLLREF Bits
PLLCFG[0]
PLLCFG[1]
MODE/
CLKCFG[2]
PLLSEL/
CLKCFG[1]
PLLREF/
CLKCFG[0]
0
0
PLL Off mode
0
X
X
0
1
Normal mode with external reference
1
1
0
1
0
Normal mode with crystal reference
1
1
1
1
1
Reserved
1
0
0
Summary of Contents for PXR4030
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