Flash Memory Array and Control
Freescale Semiconductor
12-19
PXR40 Microcontroller Reference Manual, Rev. 1
The following field and bit descriptions fully define the FLASH_x_AR (
).
FLASH_x_AR functions, as shown in
.
12.2.2.8
Flash Bus Interface Configuration Register (FLASH_BIUCR)
FLASH_BIUCR is used to specify operation of the dual-flash controller. This register must not be written
while executing from flash.
Array
Address Range
Operation
A
0x00_0000 - 0x07_FFFF
No change
A
0x08_0000 - 0x1F_FFFF
Logical address[17:3] =
Addr[16:4],0,ADDR[3]}
B
0x00_0000 - 0x07_FFFF
Add 0x08_0000
B
0x08_0000 - 0x1F_FFFF
Logical address[17:3] =
Addr[16:4],1,ADDR[3]}
Offset 0x0018 / 0x4018
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R SAD 0 0 0 0 0 0 0 0 0 0 0
0
0
ADDR
0 0 0
W
Reset
0
0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-9. FLASH_x_AR Register
Table 12-11. FLASH_x_AR Field Descriptions
Field
Description
0
SAD
Shadow Address. The SAD bit qualifies the address captured during an ECC Event Error, Single Bit
Correction, or State Machine operation.
The SAD register is not writable.
0 Address Captured is from Main Array Space.
1 Address Captured is from Shadow Array Space.
1–13
Reserved
14–28
ADDR[17:3]
Address. The FLASH_x_AR provides the first failing address in the event of ECC event error
(FLASH_x_MCR[EER] set), single bit correction (FLASH_x_MCR[SBC] set), as well as providing the
address of a failure that may have occurred in a state machine operation (FLASH_x_MCR[PEG]
cleared). ECC event errors take priority over single bit corrections, which take priority over state
machine errors. This is especially valuable in the event of a RWW operation, where the read senses an
ECC error or single bit correction, and the state machine fails simultaneously. This address is always a
Double Word address that selects 64 bits.
The FLASH_x_AR is writable, and can be used in the UTEST ECC Logic Check. If the ECC logic check
is enabled (FLASH_x_UT0[EIE] = 1) then the FLASH_x_AR will not update for ECC event error, single
bit correction or state machine errors.
If FLASH_x_MCR[EER] or FLASH_x_MCR[SBC] are set, the FLASH_x_AR is locked from writing.
FLASH_x_MCR[PEG] does not affect the writability of the FLASH_x_AR.
29–31
Reserved
Summary of Contents for PXR4030
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