Flash Memory Array and Control
Freescale Semiconductor
12-23
PXR40 Microcontroller Reference Manual, Rev. 1
12.2.2.10 Flash Bus Interface Configuration Register 2 (FLASH_BIUCR2)
NOTE
A reset value of 1* in
indicates that the reset value of these
registers is determined by Flash values in the shadow block. An erased
shadow block causes the reset value to be 1.
Offset: 0x0024
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
LBCFG
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
Figure 12-12. Flash Bus Interface Configuration Register 2 (FLASH_BIUCR2)
Table 12-14. FLASH_BIUCR2 Bit Field Descriptions
Field
Description
0–1
LBCFG_P0
Line Buffer Configuration. This field controls the configuration of all the line buffers in the flash bus interface
unit. The buffers can be organized as a “pool” of available resources, or with a fixed partition between
instruction and data buffers.
In all cases, when a buffer miss occurs, it is allocated to the least-recently-used buffer within the group and
the just-fetched entry then marked as most-recently-used. If the flash access is for the next-sequential line,
the buffer is not marked as most-recently-used until the given address produces a buffer hit.
This field is initialized by hardware reset to the value contained in address0x00FF_FE00 of the shadow block
of the flash array. The initial value is given in
.
This field controls the configuration of both the 4 x 128 and 4 x 256 line buffers.
00 All four buffers are available for any flash access, i.e., there is no partitioning of the buffers based on the
access type.
01 Reserved
10 The buffers are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches and
buffers 2 and 3 for data accesses.
11 The buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches and buffer
3 for data accesses.
2–31
Reserved
Summary of Contents for PXR4030
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