FlexCAN Module
24-42
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
•
Detection of a dominant bit at the 7th bit (last) of End of Frame field (Rx frames)
•
Detection of a dominant bit at the 8th bit (last) of Error Frame Delimiter or Overload Frame
Delimiter
24.4.8.3
Time Stamp
The value of the Free Running Timer is sampled at the beginning of the Identifier field on the CAN bus,
and is stored at the end of “move-in” in the TIME STAMP field, providing network behavior with respect
to time.
Note that the Free Running Timer can be reset upon a specific frame reception, enabling network time
synchronization. Refer to TSYN description in
Section 24.3.4.2, Control Register (FLEXCAN_x_CTRL).
24.4.8.4
Protocol Timing
shows the structure of the clock generation circuitry that feeds the CAN Protocol Interface
(CPI) sub-module. The clock source bit (CLK_SRC) in the FLEXCAN_x_CTRL Register defines whether
the internal clock is connected to the output of a crystal oscillator (Oscillator Clock) or to the Peripheral
(system) Clock from PLL). In order to guarantee reliable operation, the clock source should be selected
while the module is in Disable Mode (bit MDIS set in the Module Configuration Register).
Figure 24-16. CAN Engine Clocking Scheme
The crystal oscillator clock should be selected whenever a tight tolerance (up to 0.1%) is required in the
CAN bus timing. The crystal oscillator clock has better jitter performance than PLL generated clocks.
The FlexCAN module supports a variety of means to setup bit timing parameters that are required by the
CAN protocol. The Control Register has various fields used to control bit timing parameters: PRESDIV,
PROPSEG, PSEG1, PSEG2 and RJW. See
Section 24.3.4.2, Control Register (FLEXCAN_x_CTRL).
The PRESDIV field controls a prescaler that generates the Serial Clock (Sclock), whose period defines the
‘time quantum’ used to compose the CAN waveform. A time quantum is the atomic unit of time handled
by the CAN engine.
A bit time is subdivided into three segments
1
):
Peripheral Clock (PLL)
Oscillator Clock (Xtal)
CLK_SRC
Prescaler
(1 .. 256)
Sclock
CPI Clock
f
Tq
f
CANCLK
Prescaler
V
alue
Þ
-------------------------------------------------------
=
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
Page 30: ...PXR40 Microcontroller Reference Manual Rev 1 Freescale Semiconductor xxx...
Page 40: ...PXR40 Microcontroller Reference Manual Rev 1 xl Freescale Semiconductor...
Page 66: ...Memory Map PXR40 Microcontroller Reference Manual Rev 1 2 4 Freescale Semiconductor...
Page 120: ...Signal Descriptions 3 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 860: ...FlexCAN Module 24 50 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
Page 1167: ...Decimation Filter Freescale Semiconductor 28 53 PXR40 Microcontroller Reference Manual Rev 1...
Page 1168: ...Decimation Filter 28 54 Freescale Semiconductor PXR40 Microcontroller Reference Manual Rev 1...
