Deserial Serial Peripheral Interface (DSPI)
25-38
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
25.4.3.5.1
Filling the RX FIFO
The RX FIFO is filled with the received SPI data from the shift register. While the RX FIFO is not full,
SPI frames from the shift register are transferred to the RX FIFO. Every time a SPI frame is transferred to
the RX FIFO the RX FIFO Counter is incremented by one.
If the RX FIFO and shift register are full and a transfer is initiated, the RFOF bit in the DSPI_SR is asserted
indicating an overflow condition. Depending on the state of the ROOE bit in the DSPI_MCR, the data from
the transfer that generated the overflow is either ignored or shifted in to the shift register. If the ROOE bit
is asserted, the incoming data is shifted in to the shift register. If the ROOE bit is negated, the incoming
data is ignored.
25.4.3.5.2
Draining the RX FIFO
Host software or other intelligent blocks can remove (pop) entries from the RX FIFO by reading the DSPI
POP RX FIFO Register (DSPI_POPR). A read of the DSPI_POPR decrements the RX FIFO Counter by
one. Attempts to pop data from an empty RX FIFO are ignored, the RX FIFO Counter remains unchanged.
The data returned from reading an empty RX FIFO is undetermined.
When the RX FIFO is not empty, the RX FIFO Drain Flag (RFDF) in the DSPI_SR is set. The RFDF bit
is cleared when the RX_FIFO is empty and the DMA controller indicates that a read from DSPI_POPR is
complete or by host software writing a ‘1’ to the RFDF.
25.4.4
Deserial Serial Interface (DSI) Configuration
The DSI Configuration supports pin count reduction by serializing Parallel Input signals or register bits
and shifting them out in a SPI-like protocol. The timing and transfer protocol is described in
Section 25.4.7, Transfer Formats
. The received serial frames are converted to a parallel form (deserialized)
and placed on the Parallel Output signals or in a register. The various features of the DSI Configuration
are set in DSPI DSI Configuration Register (DSPI_DSICR). The DSPI is in DSI Configuration when the
DCONF field in the DSPI_MCR is 0b01.
The DSI frames can be from four to sixteen bits long, but four to 32 bits can be used in the TSB
configuration (see
Section 25.4.9, Timed Serial Bus (TSB)
, for detailed information). With Multiple
Transfer Operation (MTO) the DSPI supports serial chaining of DSPI blocks within a device to create DSI
frames consisting of concatenated bits from multiple DSPIs. The DSPI also supports parallel chaining
allowing several DSPIs and off-chip SPI devices to share the same Serial Communications Clock (SCK)
and Peripheral Chip Select (PCS) signals. See
Section 25.4.4.6, Multiple Transfer Operation (MTO)
, for
details on the serial and parallel chaining support.
25.4.4.1
DSI Master Mode
In DSI Master Mode the DSPI initiates and controls the DSI transfers. The DSI Master has four different
conditions that can initiate a transfer:
•
Continuous
•
Change in data
•
Trigger signal
Summary of Contents for PXR4030
Page 1: ...PXR40 Microcontroller Reference Manual Devices Supported PXR4030 PXR4040 PXR40RM Rev 1 06 2011...
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