Enhanced Serial Communication Interface (eSCI)
Freescale Semiconductor
26-35
PXR40 Microcontroller Reference Manual, Rev. 1
The TXDIR bit (eSCI_CR2[1]) determines whether the TXD pin is going to be used as an input (TXDIR
= 0) or an output (TXDIR = 1) in this mode of operation.
26.4.5.3.5
Loop Mode
In Loop Mode, the input of the receiver is driven by the output of the transmitter. The RXD pin is
disconnected from the eSCI module.
Figure 26-30. Loop Mode
26.4.5.3.6
Frame and Character Reception
The receiver is started when it is in Ready or Wakeup state and on the selected receiver input (see
Section 26.4.5.3.2, Receiver Input Mode Selection
) an active signal is sampled. The receiver enters the
Run or Wakeup state. The received bits are recovered by the bit sampling described in
. During the reception, the received bits are shifted into the internal shift register.
26.4.5.3.7
Break Character Detection
The receiver does not provide any means to detect the reception of a break character. Instead, break
characters are processed as data frames. Due to the received 0 at the stop bit location, the reception of a
break character causes at least a framing error. The error reporting is performed as described in
Section 26.4.5.4, Reception Error Reporting
26.4.5.3.8
Idle Character Detection
The start point of the idle character detection is controlled by the idle line type bit ILT in the
If the ILT bit is 0, the idle character detection starts always immediately after the reception of a bit with
the value 0. In this mode, a data frame with a payload section of all ones will be erroneously detected as
an idle character.
If the ILT bit is 1, the idle character detection starts after the reception of the last stop bit.
26.4.5.3.9
CPU Controlled SCI Data Frame Reception
This section describes the reception process when the receiver is in the Run state.
When the required number of frame bits have been received, the payload bits of the received frame are
transferred into
if the RDRF flag is 0. The receive data register full flag
RDRF in
Interrupt Flag and Status Register 1 (eSCI_IFSR1)
is set. If the receive interrupt enable bit RIE
Interrupt Flag and Status Register 1 (eSCI_IFSR1)
is set, the RDRF interrupt request is generated.
TRANSMITTER
RECEIVER
RXD
TXD
Summary of Contents for PXR4030
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