229
CHAPTER 11 MULTIFUNCTIONAL TIMER
11.4.6
Compare Control Register
(OCSH0 to OCSH5, OCSL0 to OCSL5)
The compare control register is used to control the output level, output enable, output
level reverse mode, compare operation enable, compare match interrupt enable, and
compare match interrupt flag of RT0 to RT5.
■
Compare Control Register, Upper Byte (OCSH1, OCSH3, OCSH5)
Output level bit
OTD0
Read
Write
0
RT0,RT2, or RT4 output ”0”
1
Count output value of RT0,RT2,
or RT4
RT0,RT2, or RT4 output ”1”
Output level bit
OTD1
Read
Write
0
RT1,RT3, or RT5 output ”0”
1
Count output value of RT1,RT3,
or RT5
RT1,RT3, or RT5 output ”1”
OTE0
Output enable bit
0
General-purpose I/O port
1
Waveform generator output pin (RTO0,RTO2,RTO4)
OTE1
Output enable bit
0
General-purpose I/O port
1
Waveform generator output pin (RTO1,RTO3,RTO5)
Output level reserve mode bit
CMOD
MOD1x=0
MOD1x=1
0
1
BTS0
Buffer transition selection bit
0
1
BTS1
Buffer transition selection bit
0
1
-
BTS1
BTS0
CMOD
OTE1
OTE0
OTD1
OTD0
OCSH1,OCSH3,OCSH5
Address: 00009C
H
00009E
H
0000A0
H
Compare control register (Upper)
-
R/W: Readable/Writable
-: Unused
RT0,RT2,RT4: This level is reversed immediately at
the match
w
ith compare register 0,2,4 occurs
RT1,RT3,RT5: This level is reversed immediately at
the match
w
ith compare register 1,3,5 occurs
Set "1" at match in up count mode.
Reset "0" at match in do
w
n count mode.
Reset "0" at match in up count mode.
Set "1" at match in do
w
n count mode.
RT0,RT2,RT4: This level is reversed immediately at
the match
w
ith compare register 0,2,4 occurs
RT1,RT3,RT5: This level is reversed immediately at
the match
w
ith compare register (0 or 1),(2 or
3),(4 or 5) occurs
Transfer starts
w
hen zero detection occurs (ch 0, ch 2, ch 4)
Transfer starts
w
hen compare clear match occurs (ch 0, ch 2, ch 4)
Transfer starts
w
hen compare clear match occurs (ch 1, ch 3, ch 5)
Transfer starts
w
hen zero detection occurs (ch 1, ch 3, ch 5)
Initial value: X1100000
B
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X= 0 to 5
: Initial value
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......