306
CHAPTER 13 UART
■
Block Diagram
R-
bus
Control
s
ign
a
l
S
end interr
u
pt
(to CPU)
Receive interr
u
pt
(to CPU)
S
CK (clock)
S
IN (receive d
a
t
a
)
Extern
a
l clock
S
CK
From U-TIMER
S
MR
regi
s
ter
DMA receive error
occ
u
rrence
s
ign
a
l
(to DMAC)
S
IDR
Receiving
end
s
S
ending
s
t
a
rt
s
PE
ORE
FRE
RDRF
TDRE
BD
S
RIE
TIE
PEN
P
S
BL
CL
A/D
REC
RXE
TXE
MD1
MD0
C
S
0
S
CKE
Control
s
ign
a
l
Receive
s
hifter
Receive p
a
rity
co
u
nter
Receive
b
it
co
u
nter
S
end clock
Receive clock
Receive
s
t
a
t
us
deci
s
ion circ
u
it
Receive control
circ
u
it
S
t
a
rt
b
it detection
circ
u
it
Clock
s
election
circ
u
it
S
end p
a
rity
co
u
nter
S
end
b
it co
u
nter
S
end control
circ
u
it
S
end
s
t
a
rt circ
u
it
S
ODR
S
OT (
s
end d
a
t
a
)
S
end
s
hifter
S
CR
regi
s
ter
SS
R
regi
s
ter
Summary of Contents for FR60Lite
Page 3: ......
Page 5: ......
Page 115: ...100 CHAPTER 3 CPU AND CONTROL UNITS ...
Page 127: ...112 CHAPTER 4 I O PORTS ...
Page 143: ...128 CHAPTER 5 INTERRUPT CONTROLLER ...
Page 155: ...140 CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ...
Page 197: ...182 CHAPTER 9 PPG Programmable Pulse Generator ...
Page 337: ...322 CHAPTER 13 UART ...
Page 417: ...402 CHAPTER 16 DMAC DMA Controller ...
Page 445: ...430 CHAPTER 17 FLASH MEMORY ...
Page 451: ...436 CHAPTER 18 SERIAL PROGRAMMING CONNECTION ...
Page 493: ...478 APPENDIX F Precautions on Handling ...
Page 494: ...479 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 507: ...492 INDEX ...
Page 509: ......