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CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER
13.4
Interrupt of 8/16-bit Up/Down Counter/Timer
The interrupt of the 8/16-bit up/down counter/timer occurs when the count direction is
changed only once during count start, when an match of comparison result is
detected, or when the overflow/underflow occurs.
The DMA transfer and extended intelligent I/O service (EI
2
OS) cannot be activated for
the interrupt of the 8/16-bit up/down counter/timer.
■
Interrupt of 8/16-bit up/down counter/timer
Table 13.4-1 shows the interrupt control bit and interrupt source of the 8/16-bit up/down counter/
timer.
●
Count direction change interrupt
The operation for generating the count direction change interrupt is shown below.
•
Bit14: CDCF flag of the counter control register (CCRH0/1) is set to "1".
•
While bit13: CFIE of the interrupt request (CCRH 0/1) is enabled ("1"). When the count
direction is changed only once during count start, the interrupt occurs.
●
Overflow/underflow interrupt
The operation for generating the overflow/underflow interrupt is shown below.
•
Bit5: UDIE flag of the counter status register (CSR0/1) is set to "1".
•
If bit3: OVFF or bit2: UDFF of the counter status register (CSR0/1) is set to "1", the interrupt
request occurs.
●
Counter compare match interrupt
The operation for generating the compare interrupt is shown below.
•
Bit6: CITE flag of the counter status register (CSR0/CSR1) is set to "1".
•
When a comparison result between the UDCR value and RCR value using bit4: CMPF of the
counter status register (CSR0/1) matches, the interrupt request occurs.
Table 13.4-1 Interrupt of 8/16-bit Up/Down Counter/Timer
Count direction
detection interrupt
Overflow/
underflow interrupt
Counter compare
match interrupt
Interrupt request flag
CCRH0: CDCF (bit14) ch.0
CCRH1: CDCF (bit14) ch.1
CSR0: OVFF (bit3) ch.0
UDFF (bit2)
CSR1: OVFF (bit3) ch.1
UDFF (bit2)
CSR0: CMPF (bit4) ch.0
CSR1: CMPF (bit4) ch.1
Interrupt request output
enable bit
CCRH0: CFIE (bit13) ch.0
CCRH1: CFIE (bit13) ch.1
CSR0: UDIE (bit5) ch.0
CSR1: UDIE (bit5) ch.1
CSR0: CITE (bit6) ch.0
CSR1: CITE (bit6) ch.1
Interrupt generation source
Up/down counter
direction detection
Overflow/underflow detec-
tion
Match between value of
up/down counter and that of
reload/compare register
CCRH0/OCR0 correspond to up/down counter pins (AIN0/BIN0/ZIN0).
CCRH1/OCR1 correspond to up/down counter pins (AIN1/BIN1/ZIN1).
Summary of Contents for MB90480 Series
Page 2: ......
Page 4: ......
Page 10: ...vi ...
Page 128: ...106 CHAPTER 4 RESET ...
Page 174: ...152 CHAPTER 6 LOW POWER CONSUMPTION MODE ...
Page 198: ...176 CHAPTER 7 MODE SETTING ...
Page 220: ...198 CHAPTER 9 TIMEBASE TIMER ...
Page 238: ...216 CHAPTER 11 WATCH TIMER ...
Page 280: ...258 CHAPTER 12 16 BIT INPUT OUTPUT TIMER ...
Page 406: ...384 CHAPTER 17 8 10 BIT A D CONVERTER ...
Page 478: ...456 CHAPTER 20 CHIP SELECTION FACILITY ...
Page 494: ...472 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ...
Page 498: ...476 CHAPTER 22 ROM MIRROR FUNCTION SELECTION MODULE ...
Page 526: ...504 CHAPTER 23 2M 3M BIT FLASH MEMORY ...
Page 536: ...514 CHAPTER 24 EXAMPLES OF MB90F481B MB90F482B MB90F488B MB90F489B SERIAL PROGRAMMING ...
Page 570: ...548 CHAPTER 25 PWC TIMER ONLY MB90485 SERIES ...
Page 688: ......