IDT About This Manual
Register Terminology
PES12N3 User Manual
3
June 7, 2006
Notes
Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition
Register Terminology
Software in the context of this register terminology refers to modifications made by PCIe root configura-
tion writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initial-
ization. See Table 2.
Type
Abbreviation
Description
Hardware Initialized
HWINIT
Register bits are initialized by firmware or hardware mechanisms
such as pin strapping or serial EEPROM. (System firmware hard-
ware initialization is only allowed for system integrated devices.) Bits
are read-only after initialization and can only be reset (for write-once
by firmware) with reset.
Read Only and Clear
RC
Software can read the register/bits with this attribute. Reading the
value will automatically cause the register/bit to be reset to zero.
Writing to a RC location has no effect.
Read Clear and Write
RCW
Software can read the register/bits with this attribute. Reading the
value will automatically cause the register/bits to be reset to zero.
Writes cause the register/bits to be modified.
Reserved
Reserved
The value read from a reserved register/bit is undefined. Thus, soft-
ware must deal correctly with fields that are reserved. On reads, soft-
ware must use appropriate masks to extract the defined bits and not
rely on reserved bits being any particular value. On writes, software
must ensure that the values of reserved bit positions are preserved.
That is, the values of reserved bit positions must first be read,
merged with the new values for other bit positions and then written
back.
Read Only
RO
Software can only read registers/bits with this attribute. Contents are
hardwired. Writing to a RO location has no effect.
Read Only and set by
Hardware
ROS
Software can only read registers/bits with this attribute. Contents are
set by hardware and may change. Writing to a ROS location has no
effect.
Read and Write
RW
Software can both read and write bits with this attribute.
Table 2 Register Terminology (Sheet 1 of 2)
0
1
2
3
bit 0
bit 31
Address of Bytes within Words: Big Endian
3
2
1
0
bit 0
bit 31
Address of Bytes within Words: Little Endian
Summary of Contents for 89HPES12N3
Page 10: ...IDT Table of Contents PES12N3 User Manual iv June 7 2006 Notes...
Page 14: ...IDT List of Figures PES12N3 User Manual viii June 7 2006 Notes...
Page 36: ...IDT Clocking Reset and Initialization Reset PES12N3 User Manual 2 8 June 7 2006 Notes...
Page 40: ...IDT Link Operation Slot Power Limit Support PES12N3 User Manual 3 4 June 7 2006 Notes...
Page 50: ...IDT Switch Operation Switch Core Errors PES12N3 User Manual 4 10 June 7 2006 Notes...
Page 54: ...IDT Power Management Active State Power Management PES12N3 User Manual 5 4 June 7 2006 Notes...
Page 62: ...IDT Hot Plug and Hot Swap Hot Swap PES12N3 User Manual 6 8 June 7 2006 Notes...
Page 78: ...IDT SMBus Interfaces Slave SMBus Interface PES12N3 User Manual 7 16 June 7 2006 Notes...
Page 148: ...IDT Test and Debug SerDes Test Clock PES12N3 User Manual 10 6 June 7 2006...
Page 158: ...IDT JTAG Boundary Scan Usage Considerations PES12N3 User Manual 11 10 June 7 2006 Notes...
