ÊÀÑÊÎÄ
9
CANPC527D
Chapter 3 - Hardware discription describes the major features of the CANPC527D: the Intel 82527
CAN bus controller, Galvanic isolation of the CAN-bus.
Figure 3-1 shows the general block diagram of the CANPC527D. This chapteer describes the major
features of the CANPC527D: the Intel 82527 CAN-bus controller, Galvanic isolation of the CAN-bus,
the Fiberoptic interface, the Onboard configuration EEPROM, and Digital I/O.
Fig. 3-1. CANPC527D Block diagram
82527 CAN bus controller
Reference note:
(Intel publication CAN Architectural Overview, Automotive Products Databook)
The 82527 CAN controller consists of six functional block. The CPU interface logic manages the
communication to the host computer. The CAN controller interface to the CAN bus and implements the
protocol rules of the CAN protocol for the transmission and reception of messages. The RAM is the
physical interface layer between the host CPU and the CAN bus. One eight bit I/O port provides low
speed I/O capabilities.
The 82527 RAM provides storage for 15 message objects of 8 byte length. Each message object has a
unique identifier and can be configured to either transmit of to receive except for the last message object.
The last message object is a receive-only buffer with a special mask design to allow selected groups of
different message identifiers to be received.
Each message identifier contains control and status bits. A message object with a direction set for receive
will send a remote frame by requesting a message transmission. A message set as transmit will be configured
to automatically send a data frame whenever a remote frame with a matching identifier is received over the
CAN bus. All message objects have separate transmit and receive interrupt and status bits, allowing the
CPU full flexibility in detecting when a remote frame has been sent or received.
CHAPTER 3 - HARDWARE DESCRIPTION
