CrossLink Programming and Configuration Usage Guide
Technical Note
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FPGA-TN-02014-1.2
15
MOSI
The MOSI is a dual function bi-directional pin. The direction depends upon whether a Master or Slave mode is active.
The SI/SISPI is an input data pin when using the Slave SPI mode and is an output data pin when using the Master SPI
mode. In Master SPI mode, CrossLink drives MOSI until all configuration data bytes have been loaded, at which time
the MOSI enters a high impedance state.
At least one of the sysCONFIG preferences, MASTER_SPI_PORT or SLAVE_SPI_PORT, must be set to ENABLE in order to
preserve this pin as MOSI and allow access to the SPI interface.
MISO
The MISO pin is a dual function bi-directional pin. The direction depends upon whether a Master or Slave mode is
active. The MISO is an input data pin when using the Master SPI mode and is an output data pin when using the Slave
SPI mode.
At least one of the sysCONFIG preferences, MASTER_SPI_PORT or SLAVE_SPI_PORT, must be set to ENABLE in order to
preserve this pin as SO/SPISO and allow access to the SPI interface.
CRESET_B
CRESET_B is a configuration reset pin. When CRESETB is asserted through a HIGH to LOW transition, the FPGA exits
User Mode and starts a device configuration sequence at the Initialization phase, as described in this Tech Note.
Holding the CRESETB pin LOW prevents CrossLink from leaving the Initialization phase. An external SPI Master can also
write the Activation Key to the FPGA during this LOW time to enter slave configuration mode.
4.10.3.
I
2
C Configuration Port Pins
SCL
CrossLink provides an I
2
C configuration port. The SCL is the bi-directional I
2
C Serial Clock pin, and is used to initiate and
time transactions on the I
2
C bus. SCL requires an external pull-up resistor in order to operate.
The SCL pin is available as a user I/O when CrossLink is in the Feature Row HW Default Mode state. You must ENABLE
the I2C_PORT for the configuration access to continue to be available in User Mode (see the
section on page 19 for details.) The SCL pin becomes a general purpose I/O if you do not ENABLE the I2C_PORT. The
configuration SCL pin is not shared with the I2C0 USER_SCL pin. The I2C0 and I2C1 User Mode I2C blocks operate
independently of the configuration I2C block.
SDA
The SDA pin is the I
2
C serial data input/output pin. It is bi-directional, open-drain, and requires an external pull-up
resistor in order to operate. The pin changes direction dynamically during data transactions on the I
2
C bus. The current
state depends on the current bus master and the operation being performed by that master.
The SDA pin is available as a user I/O when CrossLink is in the Feature Row HW Default Mode state. You must ENABLE
the I2C_PORT for the configuration access to be available in User Mode (see the
details.) The SDA pin becomes a general purpose I/O if you do not ENABLE the I2C_PORT. The configuration SDA pin is
not shared with the I2C0 USER_SDA pin.
