iCE40 SPRAM Usage Guide
Technical Note
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TN1314-1.0
4.4.
Cascading Memories
Each SPRAM block is 256 kb, supporting configuration that are 16K x 16. These memories are cascaded to form larger
memory based on the user requirements. The memories can be cascaded in two ways:
Address Cascading or
Data Cascading.
The following sections provide examples of how each cascading type is achieved, and the connection of the signals
required. User can instantiate the RAM primitive and connect them using this as guidance to create larger memory
blocks.
Auto cascading is supported while inferring a RAM. Any additional logic required will be implemented in the device
fabric for creating larger memories.
Address Cascading (or Depth Cascading)
4.4.1.
Address/Depth cascading is useful when the memories are required to have the capacity of storing “more” words while
keeping the data width the same. In this case additional user logic is needed to decode the address.
shows an example of the depth cascading of a 32K x 16 SPRAM. Additional logic is required that will guide
the data to the correct memory block using Muxes and Demuxes. The rest of the signals (that are not shown), should
be connected to both the memory blocks without any other logic requirements.
Single Port RAM
Primitive
SB_SPRAM256KA
ADDRESS [13:0]
DATAIN [15:0]
WREN
MASKWREN [3:0]
CHIPSELECT
CLOCK
STANDBY
SLEEP
POWEROFF
DATAOUT [15:0]
Single Port RAM
Primitive
SB_SPRAM256KA
ADDRESS [13:0]
DATAIN [15:0]
WREN
MASKWREN [3:0]
CHIPSELECT
CLOCK
STANDBY
SLEEP
POWEROFF
DATAOUT [15:0]
1
0
1
0
DATAOUT [15:0]
1
0
ADDRESS [14:0]
DATAIN [15:0]
WREN
MASKWREN [3:0]
CHIPSELECT
CLOCK
STANDBY
SLEEP
POWEROFF
ADDRESS [14]
ADDRESS [13:0]
Figure 4.1. Address/Depth Cascading Example for 32K x 16 SPRAM using Primitive
