iCE40 SPRAM Usage Guide
Technical Note
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TN1314-1.0
9
Data Cascading (or Width Cascading)
4.4.2.
Data/Width cascading is useful when the memories are required to have the capacity of storing “longer” words while
keeping the address depth the same. In this case, very minimal user logic is needed, essentially for concatenating
words from individual SPRAM blocks.
shows an example of the Width cascading of a 16k x 32 SPRAM. The rest of the signals (that are not shown),
should be connected to both the memory blocks without any other logic requirements.
Single Port RAM
Primitive
SB_SPRAM256KA
ADDRESS [13:0]
DATAIN [15:0]
WREN
MASKWREN [3:0]
CHIPSELECT
CLOCK
STANDBY
SLEEP
POWEROFF
DATAOUT [15:0]
DATAOUT [31:0]
ADDRESS [13:0]
DATAIN [31:0]
WREN
MASKWREN [7:0]
CHIPSELECT
CLOCK
STANDBY
SLEEP
POWEROFF
Single Port RAM
Primitive
SB_SPRAM256KA
ADDRESS [13:0]
DATAIN [15:0]
WREN
MASKWREN [3:0]
CHIPSELECT
CLOCK
STANDBY
SLEEP
POWEROFF
DATAOUT [15:0]
DATAIN [31:16]
MASKWREN [7:4]
DATAIN [15:0]
MASKWREN [3:0]
DATAOUT [31:16]
DATAOUT [15:0]
Figure 4.2. Data/Width Cascading Example for 16K x 32 SPRAM using Primitive
