MAX32600 User’s Guide
Communication Peripherals
7.1 I²C
I²C and SMBus Compliance
SMBus and I
2
C protocols are essentially the same: an SMBus master is able to control I
2
C devices and vice versa at the protocol level. The SMBus clock is defined
from 10kHz to 100kHz whereas I
2
C can range from 0Hz to 100kHz or 0Hz to 400kHz depending on the mode. An I
2
C bus running at less than 10kHz is not SMBus
compliant since the SMBus device(s) may time out (see
below).
Peripheral Management Unit
The I
2
C supports direct memory access peripheral communication via the
Peripheral Management Unit (PMU)
. This allows the PMU to read and/or write the FIFOs
of the I
2
C device.
To enable the PMU transfers, reference
Peripheral Management Unit (PMU)
. There is no additional configuration for the I
2
C device: the PMU should be seen as
a core (executing software) replacement. The I
2
C interrupts are not rerouted to the PMU and are still routed to the core (it is up to the software to configure the
interrupts according to the PMU usage).
Rx FIFO
Rx FIFO transfers are 8-byte depth. The Rx FIFO is written by hardware when a data has been received from the device. If the Rx FIFO is full, all data received from
the slave are lost; a new read operation cannot be started with the Rx FIFO full. Reading the data register is necessary to read the Rx FIFO.
Tx FIFO
Tx FIFO transfers are 8-byte depth. The Tx FIFO is written by software using the data register (a write in the data register writes into the Tx FIFO). The Tx FIFO is
read by hardware only when the acknowledge bit has been received (meaning just before the stop/restart bit in case of NACK or just before the first bit of the next
data in case of ACK).
Timeout Feature
The SMBus protocol has a timeout feature which resets devices if communication takes too long. The minimum clock frequency of 10kHz for SMBus peripherals
prevents locking up the bus erroneously. The I
2
C can be a DC bus, meaning that a slave device stretches the master clock when performing some routine while
the master is accessing it. This notifies the master that the slave is busy but does not want to lose communication. The slave device will allow continuation of the
communication after its task is complete. There is no limit to the delay in the I
2
C bus protocol; for a SMBus system, the delay is limited to 35ms. SMBus protocol
assumes if a communication takes too long, there must be a problem on the bus and all devices must reset in order to clear this mode. This is the timeout feature of
the SMBus. Slave devices are not then allowed to hold the clock in the low state too long.
Rev.1.3 April 2015
Maxim Integrated
Page 229
