Motorola CPU32, Reference Manual

Page 1: ...M68300 Family CP 32RM AD REV I CENTRAL PROCESSOR UNIT REFERENCE MANUAL MOTOROLA ...

Page 2: ... in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fe...

Page 3: ......

Page 4: ...tion refer to an active or true signal Negate and negation refer to an inactive or false signal These terms are used independently of the voltage level that they represent This manual is written for systems designers systems programmers and applications programmers Systems designers need general knowledge of the entire volume with particular emphasis on Section 1 Section 7 and Appendix A they will...

Page 5: ...MOTOROLA iv CPU32 REFERENCE MANUAL ...

Page 6: ...able Lookup and Interpolate Instructions 1 5 Low Power Stop Instruction 1 7 Processing States 1 7 Privilege States 1 7 Block Diagram 1 8 Section 2 Architecture Summary Programming ModeL 2 1 Registers 2 3 Data Types 2 4 Organization in Registers 2 4 Data Registers 2 4 Address Registers 2 6 Control Registers 2 6 Organization in Memory 2 7 Section 3 Data Organization and Addressing Capabilities Progr...

Page 7: ...acement 3 9 Program Counter Indirect with Index Base Displacement 3 9 Absolute Short Address 3 1 0 Absolute Long Address 3 11 Immediate Data 3 11 Effective Address Encoding Summary 3 12 Programming View of Addressing Modes 3 14 Addressing Capabilities 3 15 General Addressing Mode Summary 3 16 M68000 Family Addressing Capability 3 18 Other Data Structures 3 19 System Stack 3 19 User Stacks 3 20 Que...

Page 8: ... 5 2 Supervisor Privilege Level 5 2 User Privilege Level 5 2 Changing Privilege Level 5 3 Types of Address Space 5 3 CPU Space Access 5 4 Type 0000 Breakpoint 5 5 Type 0001 MMU Access 5 5 Type 0010 Coprocessor Access 5 5 Type 0011 Internal Register Access 5 5 Type 1111 Interrupt Acknowledge 5 6 Section 6 Exception Processing 6 1 Definition of Exception Processing 6 1 6 1 1 Exception Vectors 6 1 6 ...

Page 9: ... 23 Type II Correcting Faults via RTE 6 24 Type III Correcting Faults via Software 6 24 Type III Correcting Faults by Conversion and Restart 6 25 Type III Correcting Faults via RTE 6 25 Type IV Correcting Faults via Software 6 25 CPU32 Stack Frames 6 26 Normal Four Word Stack Frame 6 26 Normal Six Word Stack Frame 6 27 BERR Stack Frame 6 27 Section 7 Development Support CPU32 Integrated Developmen...

Page 10: ...l Memory Block FILL 7 26 Resume Execution GO 7 27 Call User Code CALL 7 28 Reset Peripherals RST 7 30 No Operation NOP 7 31 Future Commands 7 31 Deterministic Opcode Tracking 7 32 Instruction Fetch IFETCH 7 32 Instruction Pipe IPIPE 7 32 Opcode Tracking during Loop Mode 7 34 Section 8 Instruction Execution Timing Resource Scheduling 8 1 Microsequencer 8 1 Instruction Pipeline 8 2 Bus Controller Re...

Page 11: ...cal Instructions 8 18 Immediate Arithmetic Logical Instructions 8 20 Binary Coded Decimal and Extended Instructions 8 21 Single Operand Instructions 8 22 Shift Rotate Instructions 8 23 Bit Manipulation Instructions 8 24 Conditional Branch Instructions 8 25 Control Instructions 8 26 Exception Related Instructions and Operations 8 27 Save and Restore Operations 8 28 Appendix A M68000 Family Summary ...

Page 12: ...rds 3 17 4 1 Instruction Word General Format 4 3 4 2 Instruction Description Format 4 19 4 3 Table Example 1 4 196 4 4 Table Example 2 4 197 4 5 Table Example 3 4 199 6 1 Exception Stack Frame 6 4 6 2 Reset Operation Flowchart 6 7 6 3 Format 0 Four Word Stack Frame 6 27 6 4 Format 2 Six Word Stack Frame 6 28 6 5 Internal Transfer Count Register 6 28 6 6 Format C BERR Stack for Prefetches and Opera...

Page 13: ...2 Command Sequence Diagram Example 7 15 Functional Model of Instruction Pipeline 7 34 Instruction Pipeline Timing Diagram 7 35 Block Diagram of Independent Resources 8 2 Simultaneous Instruction Execution 8 4 Attributed Instruction Times 8 5 Example 1 Instruction Stream 8 8 Example 2 Branch Taken 8 8 Example 2 Branch Not Taken 8 9 Example 3 Branch Negative Tail 8 10 CPU32 REFERENCE MANUAL ...

Page 14: ...2 4 6 Bit Manipulation Operations 4 13 4 7 Binary Coded Decimal Operations 4 13 4 8 Program Control Operations 4 14 4 9 System Control Operations 4 15 4 10 Condition Tests 4 17 4 11 Operation Cpde Map 4 1 75 5 1 Address Spaces 5 4 6 1 Exception Vector Assignments 6 2 6 2 Exception Priority Groups 6 5 6 3 Tracing ControL 6 13 7 1 BOM Source Summary 7 4 7 2 Polling the BOM Entry Source 7 6 7 3 CPU G...

Page 15: ...MOTOROLA xiv CPU32 REFERENCE MANUAL ...

Page 16: ...inately register memory interaction philosophy All data resources are available to all operations requiring those resources There are eight multifunction data registers and seven general purpose addressing registers The data registers readily support 8 bit byte 16 bit word and 32 bit long word operand lengths for all operations Address manipulation is supported by word and long word operations Alt...

Page 17: ...7 MHz Operating Frequency 40 to 125 C Fully Static Implementation 1 1 1 Virtual Memory A system that supports virtual memory has a limited amount of high speed physical memory that can be accessed directly by the processor and maintains an image of a much larger virtual memory on a secondary storage device When the processor attempts to access a location in the virtual memory map that is not resid...

Page 18: ...erations The CPU automatically exits loop mode for interrupts or other exceptions ONE WORD INSTRUCTION DSce OSee DISPLACEMENT r FFFC 4 Figure 1 1 Loop Mode Instruction Sequence 1 1 3 Vector Base Register The vector base register VBR contains the base address of the 1024 byte exception vector table The table contains 256 exception vectors Exception vectors are the memory addresses of routines that ...

Page 19: ... occurs To support generic handlers the processor also places the vector offset in the exception stack frame and marks the frame with a format code The return from exception RTE instruction uses the format code to determine what information is on the stack so that context can be properly restored 1 1 5 Enhanced Addressing Modes Addressing in the CPU32 is register oriented Most instructions allow t...

Page 20: ...structions and illegal effective addressing modes allowing the user to emulate instructions or to define special purpose functions However Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 core enhancements See SECTION 4 INSTRUCTION SET for comprehensive information 1 1 6 1 Table Lookup and Interpolation Instructions To speed up real time ...

Page 21: ...t OR Logical Inclusive OR ORI Logical Inclusive OR Check Register Against Immediate Upper and Lower Bounds PEA Push Effective Address Clear RESET Reset External Devices Compare Compare Address Compare Immediate Compare Memory to Memory ROL ROR Rotate Left and Right ROXL ROXR Rotate with Extend Left and Right RID Return and Deallocate Compare Register Against Upper and Lower Bounds RTE Return from ...

Page 22: ...ap instructions tracing and other exception conditions Background processing allows interactive debugging of the system Halted processing is an indication of catastrophic hardware failure See SECTION 5 PROCESSING STATES for complete information 1 1 8 Privilege States The processor can operate at either of two privilege levels Supervisor level is more privileged than user level all instructions are...

Page 23: ...tions prior to execution The execution unit maintains the program counter and performs required operations under sequencer control The bus control contains a write pending buffer that allows the sequencer to continue execution of instructions after a request for a write cycle is queued See SECTION 8 INSTRUCTION EXECUTION TIMING for a detailed explanation of instruction execution DATA BUS ADDRESS B...

Page 24: ...parate Program and Data Address Spaces Many Data Types Flexible Addressing Modes Full Interrupt Processing Expansion Capability 2 1 Programming Model The CPU32 programming model consists of two groups of registers that correspond to the user and supervisor privilege levels User programs can only use the registers of the user model The supervisor programming model which supplements the user program...

Page 25: ...ER STACK POINTER 0 I PC PROGRAM COUNTER 15 8 7 0 0 I CCR CONDITION CODE REGISTER Figure 2 1 User Programming Model 16 15 0 I AT SSP SUPERVISOR STACK POINTER 15 8 7 0 CCR ISR STATUS REGISTER 0 I PC PROGRAM COUNTER 3 2 0 ISFC ALTERNATE FUNCTION CODE REGISTERS DFC Figure 2 2 Supervisor Programming Model Supplement ARCHITECTURE SUMMARY CPU32 REFERENCE MANUAL ...

Page 26: ...on execution and exception processing the processor automatically increments the contents of the PC or places a new value in the PC as appropriate The status register SR see Figure 2 3 contains condition codes an interrupt priority mask three bits and three control bits Condition codes reflect the results of a previous operation The codes are contained in the low byte or condition code register of...

Page 27: ...s 64 bits 2 3 1 Organization in Registers The eight data registers can store data operands of 1 8 16 32 and 64 bits and addresses of 16 or 32 bits The seven address registers and the two stack pointers are used for address operands of 16 or 32 bits The PC is 32 bits wide 2 3 1 1 Data Registers Each data register is 32 bits wide Byte operands occupy the low order 8 bits word operands the low order ...

Page 28: ...erations signed and unsigned Quad words may be organized in any two data registers without restrictions on order or pairing There are no explicit instructions for the management of this data type however the MOVEM instruction can be used to move a quad word into or out of the registers BCD data represents decimal numbers in binary form CPU32 BCD instructions use a format in which a byte contains t...

Page 29: ...tion for supervisor functions The registers vary in size With the exception of the user portion of the SR CCR they are accessed only by instructions at the supervisor privilege level The SR shown in Figure 2 3 is 16 bits wide Only 11 bits of the SR are defined and all undefined values are reserved by Motorola for future definition The undefined bits are read as zeros and should be written as zeros...

Page 30: ...nificant byte of the low order word is N 2 and the address of the 2 least significant byte of the long word is N 3 The CPU32 requires data words and long words as well as instruction words to be aligned on word boundaries Data misalignment is not supported Figure 2 6 shows how operands and instructions are organized in memory Note that N X is below N that is address value increases as one moves do...

Page 31: ...RD 0 o o o LOW ORDER LSB LONG WORD 1 LONG WORD 2 15 12 11 BCD 0 BCD 4 MSD Most Significant Digit LSD Least Significant Digit 15 MSB t ADDRESS 0 BCD 1 BCD5 DECIMAL DATA 2 BCD DIGITS 1 BYTE 8 7 LSD ADDRESS 32 BITS HIGH ORDER LOW ORDER BCD 2 BCD6 4 3 BCD3 BCD7 1 ADDRE 2 MSB Most Significant Bit LSB Least Significant Bit Figure 2 6 Memory Operand Addressing o o LSB MOTOROLA 2 8 ARCHITECTURE SUMMARY CP...

Page 32: ... that do not use registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 a EFFECTIVE ADDRESS X X X X X X X X X X MODE I REGISTER Figure 3 1 Single Effective Address Instruction Operation Word Many instructions imply the addressing mode for only one of the operands The formats of these instructions include appropriate fields for operands that use only a single addressing mode Additional information may be need...

Page 33: ... are to data space 3 2 Notation Conventions EA Effective address An Address register n Example A3 is address register 3 On Data register n Example 05 is data register 5 Rn Any register data or address Xn SIZE SCALE Index register n data or address Index size W for word L for long word Scale factor 1 2 4 or 8 for byte word long word or quad word scaling PC Program counter SR Status register SP Stac...

Page 34: ...Implicit Registers ANDIto CCR SR ANDlto SR SR BRA PC BSR PC SP CHK exception PC SP CHK2 exception SSP SR DBcc PC DIVS exception SSP SR DIVU exception SSP SR EORltoCCR SR EORltoSR SR JMP PC JSR PC SP LINK SP LPSTOP SR MOVECCR SR MOVESR SR MOVE USP USP ORltoCCR SR ORltoSR SR PEA SP RTD PC SP RTE PS SP SR Rm PC SP SR RTS PC SP STOP SR TRAP exception SSP SR TRAPV exception SSP SR UNLK SP CPU32 REFEREN...

Page 35: ...ister Direct Mode These EA modes specify that the operand is in one of the 16 multifunction registers 3 4 1 1 Data Register Direct In the data register direct mode the operand is in the data register specified by the EA register field GENERATION ASSEMBLER SYNTAX MODE REGISTER DATA REGISTER NUMBER OF EXTENSION WORDS EA Dn Dn o 0 n I__________ O_PE_R_AN_D________ I 3 4 1 2 Address Register Direct In...

Page 36: ...ointer and the operand size is byte the address is incremented by two rather than one to keep the stack pointer aligned to a word boundary GENERATION ASSEMBLER SYNTAX MODE REGISTER ADDRESS REGISTER EA An An An SIZE An 011 n 31 An I MEMORY ADDRESS r OPERAND LENGTH 1 2 OR 4 I 31 MEMORY ADDRESS NUMBER OF EXTENSION WORDS OPERAND 3 4 2 3 Address Register Indirect With Predecrement In the address regist...

Page 37: ... 3 4 2 5 Address Register Indirect With Index 8 Bit Displacement This mode requires one extension word that contains the index register indicator and an 8 bit displacement The index register indicator includes size and scale information In this mode the operand is in memory The address of the operand is the sum of the contents of the address register the sign extended displacement value in the low...

Page 38: ...l data or address register used as an index register The index operand is derived from the index register The index register is a data register if bit 15 0 in the first extension word and an address register if bit 15 1 The index register number is given by extension word bits 14 12 Index size is referred to as sz It may be either W or L Index size is given by bit 11 of the extension word If bit 1...

Page 39: ...Y ADDRESS 31 NUMBER OF EXTENSION WORDS 1 2 OR3 OPERAND 3 4 3 Special Addressing Modes These special addressing modes do not use the register field to specify a register number but rather to specify a submode 3 4 3 1 Program Counter Indirect With Displacement In this mode the operand is in memory The address of the operand is the sum of the address in the program counter and the sign extended 16 bi...

Page 40: ...he address of the extension word This reference is a program space reference and is only allowed for reads The user must include the displacement the program counter and the index register when specifying this addressing mode 3 4 3 3 Program Counter Indirect with Index Base Displacement This mode is similar to the address register indirect with index base displacement mode described in 3 4 2 6 Add...

Page 41: ...BLER SYNTAX EA PC Xn bd bd PC Xn SIZE SCALE MODE REGISTER 6n 31____________ PROGRAM COUNTER ADDRESS OF EXTENSION WORD 31 BASE DISPLACEMENT SIGN EXTENDED VALUE 31 INDEX REGISTER SIGN EXTENDED VALUE SCALE SCALE VALUE MEMORY ADDRESS 31 NUMBER OF EXTENSION WORDS 1 2 OR3 OPERAND 3 4 3 4 Absolute Short Address In this addressing mode the operand IS In memory and the address of the operand is in the exte...

Page 42: ... EXTENSION WORDS 3 4 3 6 Immediate Data EAGIVEN xxx L 111 001 15 31 31 ADDRESS HIGH OPERAND In this addressing mode the operand is in one or two extension words Byte Operation The operand is in the low order byte of the extension word Word Operation The operand is in the extension word Long Word Operation The high order 16 bits of the operand are in the first extension word the low order 16 bits a...

Page 43: ... mode when the mode field contains 111 Some indexed or indirect modes use the instruction word followed by the brief format extension word Other indexed or indirect modes consist of the instruction word and the full format of extension words The longest instruction for the CPU32 contains six extension words It is a MOVE instruction with full format extension words for both source and destination E...

Page 44: ...ng Word Displacement Indexllndirect Selection Indirect and Indexing Operand Determined in Conjunction with Bit 6 Index Suppress Memory indirect addressing will cause illegal instruction trap must be 000 if IS 1 Figure 3 2 Effective Address Specification Formats EA modes can be classified as follows Data A data addressing EA mode refers to data operands Memory A memory addressing EA mode refers to ...

Page 45: ...Indirect with Displacement Address Register Indirect with Index 8 Bit Displacemment Address Register Indirect with Index Base Displacement Absolute Short Absolute Long Program Counter Indirect with Displacement Program Counter Indirect with Index 8 Bit Displacement Program Counter Indirect with Index Base Displacement Immediate MOTOROLA 3 14 Code Register Data Memory Control Alterable Syntax 000 r...

Page 46: ...32 the register indirect modes can be extended further Because displacements can be 32 bits wide they can represent absolute addresses or the results of expressions that contain absolute addresses This scheme allows the general register indirect form to be bd Rn or bd An Rn when the base register is not suppressed Thus an absolute address can be directly indexed by one or two registers refer to Fi...

Page 47: ...erived from specific combinations of options in the indexing mode or a selection of two alternate addressing modes For example the addressing mode called register indirect Rn assembles as address register indirect if the register is an address register If Rn is a data register the assembler uses address register indirect with index mode with a data register as the indirect register and suppresses ...

Page 48: ...rray structure software increments index to point to next record Figure 3 5 Addressing Array Items It is useful to examine the derived addressing modes available to a programmer without regard to the CPU32 EA mode actually encoded because the programmer need not be concerned about these decisions The assembler can choose the more efficient addressing mode to encode CPU32 REFERENCE MANUAL DATA ORGA...

Page 49: ...on words for the early MC68000 MC68008 MC68010 and MC68020 microprocessors are shown in Figure 3 6 15 I D A I D A 14 12 REGISTER MC6800 MC68008 MC68010 ADDRESS EXTENSION WORD 11 10 9 8 7 IW L I 0 I 0 I 0 I DISPLACEMENT INTEGER o Data Register Select 1 Address Register Select W L 0 Word Sized Operation 1 Long Word Sized Operation CPU32 MC68020 EXTENSION WORD 15 14 12 11 10 9 8 7 I D A I REGISTER IW...

Page 50: ...is popped or pulled from the structure The system stack is used implicitly by many instructions user stacks and queues may be created and maintained through use of addressing modes 3 7 1 System Stack Address register 7 A7 is the system stack pOinter SP The SP is either the supervisor stack pOinter SSP or the user stack pointer USP depending on the state of the S bit in the status register If the S...

Page 51: ...er to the stack Use the postincrement mode to increment the register after its contents are used as the pointer to the stack Maintain the SP correctly when byte word and long word items are mixed in these stacks To implement stack growth from high to low memory use An to push data on the stack An to pull data from the stack For this type of stack after either a push or a pull operation register An...

Page 52: ...put data into the queue Am to get data from the queue After a put operation the put register points to the next available queue space and the unchanged get register points to the next item to be removed from the queue After a get operation the get register points to the next item to be removed from the queue and the unchanged put register points to the next available queue space which is illustrat...

Page 53: ... get operation the get register points to the last item removed from the queue and the unchanged put register points to the last item placed in the queue which is illustrated as follows LOW MEMORY FREE PUT An LAST PUT NEXT GET GET Am LAST GET FREE HIGH MEMORY To implement the queue as a circular buffer the get or put operation should be performed first and then the relevant address register should...

Page 54: ...operations Shifts and rotates Bit manipulation Conditionals and branches System control The large instruction set encompasses a complete range of capabilities and combined with the enhanced addressing modes provides a flexible base for program development 4 1 M68000 Family Compatibility It is the philosophy of the M68000 Family that all user mode programs can execute unchanged on a more advanced p...

Page 55: ...terpolation to recover intermediate values from a sample of data points and thus conserves memory When the TBL instruction is executed the CPU32 looks up two table entries bounding the desired result and performs a linear interpolation between them Byte word and long word operand sizes are supported The result can be rounded according to a round to nearest algorithm or returned unrounded along wit...

Page 56: ...DS DESTINATION EFFECTIVE ADDRESS EXTENSION IF ANY ONE TO THREE WORDS Figure 4 1 Instruction Word General Format Besides the operation code which specifies the function to be performed an instruction defines the location of every operand for the function Instructions specify an operand location in one of three ways Register specification Effective address Implicit reference A register field of the ...

Page 57: ...ters high and low order 32 bits of product Data registers division remainder division quotient Data registers used in computation Data registers table interpolation values Index register Address extension Condition code Displacement Example d16 is a 16 bit displacement Effective address Immediate data a literal integer Assembly program label List of registers Example D3 DO Bits of an operand Examp...

Page 58: ...SW R W Equal to Not equal to Greater than Greater than or equal to Less than Less than or equal to Boolean AND Boolean OR Boolean XOR exclusive OR Boolean complement operand is inverted Binary coded decimal indicated by subscript Example Source1o is a BCD source operand Least significant word Most significant word Read write indicator In description of an operation a destination operand is placed ...

Page 59: ...sult of a processor operation Table 4 1 lists the effect of each instruction on these bits The carry bit and the multiprecision extend bit are separate in the M68000 Family to simplify programming techniques that use them Refer to Table 4 5 as an example Table 4 1 Condition Code Computations Operations ABCD ADD ADDI ADDQ ADDX AND ANDI EOR EORI MCVEQ MOVE OR ORI CLR EXT NOT TAS TST CHK CHK2 CMP2 SU...

Page 60: ...m Am Sm Dm Rm C Sm Dm Rm Dm Sm Rm v Division Overflow v Multiplication Overflow C Decimal Borrow Z Z Rm RO V Dm Rm C Dm Rm V Dm Am C Dm Rm V Dm Dm 1 Dm r Dm Dm 1 Dm r C Dm r 1 o C Dm r 1 o o C Dr 1 o C Dr 1 o Note The followmg notation applies to this table only Not affected U Undefined See special definition General case X C N Rm Z Rm RO CPU32 REFERENCE MANUAL INSTRUCTION SET Sm Source operand MS...

Page 61: ... registers EXG load effective address LEA push effective address PEA link stack LINK and unlink stack UNLK Table 4 2 is a summary of the data movement operations Instruction EXG LEA LINK MOVE MOVEA MOVEM MOVEP MOVEO PEA UNLK MOTOROLA 4 8 Table 4 2 Data Movement Operations Syntax Operand Operation Size Rn Rn 32 Rn Rn ea An 32 ea An An d 16 32 SP 4 SP An SP SP An SP d SP ea ea 8 16 32 Source Destina...

Page 62: ... remainder A set of extended instructions provides multiprecision and mixed size arithmetic These instructions are add extended ADDX subtract extended SUBX sign extend EXT and negate binary with extend NEGX Refer to Table 4 3 for a summary of the integer arithmetic operations Table 4 3 Integer Arithmetic Operations Instruction Syntax ADD Dn ea ea Dn ADDA ea An ADDI data ea ADDQ data ea ADDX Dn Dn ...

Page 63: ...ation 1Source Destination 32 32 32 32 signed or unsigned 8 16 Sign extended Destination Destination 16 32 8 32 Sign extended Destination Destination 16 16 32 32 32 32 Source Destination Destination 32 32 64 signed or unsigned 8 16 32 0 Destination Destination 8 16 32 0 Destination X Destination 8 16 32 Destination Source Destination 16 32 Destination Source Destination 8 16 32 Destination Data Des...

Page 64: ...ata Destination Destination TST ea 8 16 32 Solurce 0 to set condition codes 4 3 5 Shift and Rotate Instructions The arithmetic shift instructions ASR and ASL and logical shift instructions LSR and LSL provide shift operations in both directions The ROR ROL ROXR and ROXL instructions perform rotate circular shift operations with and without the extend bit All shift and rotate operations can be perf...

Page 65: ...n Dn 8 16 32 LCIH ROXR data Dn 8 16 32 ea 16 SWAP On 16 I I I 4 3 6 Bit Manipulation Instructions Bit manipulation operations are accomplished using the following instructions bit test BT8T bit test and set B8ET bit test and clear BCLR and bit test and change BCHG All bit manipulation operations can be performed on either registers or memory The bit number is specified as immediate data or in a da...

Page 66: ...erations on packed BCD numbers are add decimal with extend ABeD subtract decimal with extend SBCD and negate decimal with extend NBCD Table 4 7 is a summary of the BCD operations Table 4 7 Binary Coded Decimal Operations Instruction Syntax Operand Operation Size ABCD Dn Dn 8 Source10 Destination1Q X Destination An An 8 NBCD ea 8 o Destination1 0 X Destination 8 SBCD Dn Dn 8 Destination10 Source10 ...

Page 67: ...e PC 2 PC Returns RID d 16 SP PC SP 4 d SP RlR SP CCR SP 2 SP SP PC none none SP 4 SP RTS none none SP PC SP 4 SP To specify conditions for change in program control condition codes must be substituted for the letters cc in conditional program control opcodes Condition test mnemonics are given below Refer to 4 3 10 Condition Tests for detailed information on condition codes CC Carry clear CS Carry...

Page 68: ...ation on condition codes Table 4 9 System Control Operations Instruction Syntax ANDI data SR EORI data SR ea SR MOVE SR ea USP An MOVEA An USP MOVEC RC Rn Rn Rc MOVES Rn ea ea Rn ORI data SR RESET none RTE none STOP data LPSTOP data CPU32 REFERENCE MANUAL Size Operation Priveleged 16 Data SR SR 16 Data Ell SR SR 16 Source SR 16 SR Destination 32 USP An 32 An USP 32 Rc Rn 32 Rn Rc 8 16 32 Rn Destin...

Page 69: ...en enter none background mode else formaVvector offset SSP PC SSP SR SSP vector PC 16 32 If Dn 0 or Dn ea then CHK exception 8 16 32 If Rn lower bound or Rn upper bound then CHK exception SSP 2 SSP vector offset SSP SSP 4 SSP PC SSP none SSP 2 SSP SR SSP lIegal instruction vector address PC SSP 2 SSP formaVvector offset SSP none SSP 4 SSP PC SSP SR SSP vector address PC none 16 32 If cc true then ...

Page 70: ...only if the Z bit condition code is true Table 4 10 lists each condition test Table 4 10 Condition Tests Mnemonic Condition Encoding T True 0000 F False 0001 HI High 0010 LS Low or Same 0011 CC Carry Clear 0100 CS Carry Set 0101 NE Not Equal 0110 EQ Equal 0111 VC Overflow Clear 1000 VS Overflow Set 1001 PL Plus 1010 MI Minus 1011 GE Greater or Equal 1100 LT Less Than 1101 GT Greater Than 1110 LE L...

Page 71: ...on applies with the following additions A The attributes line specifies the size of the operands of an instruction When an instruction can use operands of more than one size a suffix is used with the mnemonic of the instruction B Byte W Word L Long word B In instruction set descriptions changes in CCR bits are shown as follows o 1 U MOTOROLA 4 18 Set according to result of operation Not affected b...

Page 72: ...lt in the desti decimal arithmetic The operands different ways 1 Data reg ister to data register specified in the instruction 2 Memory to memory The ope addreSSing mode using the Condition Codes X N Z V C I I U I U I X Set the same as the carry bit N Undefined Z Cleared if the result is nonzero Un V Undefined C Set if a decimal carry was gene NOTE Normallythe Z condition code bit an operation This...

Page 73: ...pecified by the instruction 2 Memory to memory Operands are addressed with the predecrement addressing mode using address registers specified by the instruction Condition Codes x N z v u u X Set the same as the carry bit N Undefined c Z Cleared if the result is nonzero Unchanged otherwise V Undefined C Set if a decimal carry was generated Cleared otherwise NOTE Normally the Z condition code bit is...

Page 74: ...r predecrement addressing mode RIM field Specifies the operand addressing mode the operation is data register to data register 1 the operation is memory to memory Register Ry field Specifies the source register If RIM 0 specifies a data register If RIM 1 specifies an address register for predecrement addressing mode CPU32 REFERENCE MANUAL INSTRUCTION SET ABCD MOTOROLA 4 21 III ...

Page 75: ... size Condition Codes x N z v C X Set the same as the carry bit N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if an overflow is generated Cleared otherwise C Set if a carry is generated Cleared otherwise Instruction Format 15 14 13 12 11 10 9 8 7 1 1 0 1 REGISTER OPMODE Instruction Fields 6 Register field Specifies any of the eight data regis...

Page 76: ...f the location specified is a destination operand only memory alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC ds An Xn 110 Reg number An ds PC Xn bd An Xn 110 Reg number An bd PC Xn NOTES 1 Dn mode is used ...

Page 77: ... field Specifies the size of the operation 011 Word operation The source operand is sign extended to a long operand and the operation is performed on the address register using all 32 bits 111 Long operation Effective Address field Specifies source operand All addressing modes are allowed as shown Addressing Mode MOTOROLA 4 24 On An An An An d16 An d8 An Xn bd An Xn Mode 000 001 010 011 100 101 11...

Page 78: ...s the carry bit N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if an overflow is generated Cleared otherwise C Set if a carry is generated Cleared otherwise Instruction Format 15 14 13 12 11 10 9 8 7 0 0 0 0 0 1 1 0 SIZE WORD DATA 16 BITS 6 LONG DATA 32 BITS Instruction Fields Size field Specifies the size of the operation 00 Byte operation 01...

Page 79: ... Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC da An Xn 110 Reg number An da PC Xn bd An Xn 110 Reg number An bd PC Xn Immediate field Data immediately following the instruction If size 00 the data is the low order byte of the immediate word If size 01 the data is the entire immediate word If size 10 the data is the next two immediate words ADDI Mode Register 111 000 111 001 M...

Page 80: ... entire destination address register is used regardless of the operation size Condition Codes x N z v C X Set the same as the carry bit N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if an overflow occurs Cleared otherwise C Set if a carry occurs Cleared otherwise The condition codes are not affected when the destination is an address register...

Page 81: ...on location Only alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode On 000 Reg number On xxx W 111 An 001 Reg number An xxx L 111 An 010 Reg number An data 111 An 011 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC 111 de An Xn 110 Reg number An de PC Xn 111 bd An Xn 110 Reg number An bd PC Xn 111 Word and long only Register 000 00...

Page 82: ...struction address the operands using the predecrement addressing mode Condition Codes x N Z v c X Set the same as the carry bit N Set if the result is negative Cleared otherwise Z Cleared if the result is nonzero Unchanged otherwise V Set if an overflow occurs Cleared otherwise C Set if a carry is generated Cleared otherwise NOTE Normally the Z condition code bit is set via programming before the ...

Page 83: ...the size of the operation 00 Byte operation 01 Word operation 10 Long operation RIM field Specifies the operand address mode o The operation is data register to data register 1 The operation is memory to memory Register Ry field Specifies the source register If RIM 0 specifies a data register If RIM 1 specifies an address register for predecrement addressing mode ADDX MOTOROLA 4 30 INSTRUCTION SET...

Page 84: ...erand Condition Codes x N z v C o 0 X Not affected N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result is zero Cleared otherwise V Always cleared C Always cleared Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 a EFFECTIVE ADDRESS 1 1 0 0 REGISTER OPMODE Instruction Fields Register field Specifies any of the eight data registers Opmode field Byte 000 1...

Page 85: ... 110 Reg number An bd PC Xn 111 011 If the location specified is a destination operand only memory alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register On xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC de An Xn 110 Reg number An de PC Xn bd An Xn 110 Reg number...

Page 86: ...ondition Codes x N Z v C o 0 X Not affected N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result is zero Cleared otherwise V Always cleared C Always cleared Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o EFFECTIVE ADDRESS 0 0 0 0 0 0 1 0 SIZE WORD DATA 16 BITS LONG DATA 32 BITS Instruction Fields Size field Specifies the size of the operation 00 Byte...

Page 87: ...11 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC ds An Xn 110 Reg number An dS PC Xn bd An Xn 110 Reg number An bd PC Xn Immediate field Data immediately following the instruction If size 00 the data is the low order byte of the immediate word If size 01 the data is the entire immediate word If size 10 the data is the next two immediate words ANDI Mode Register 111 000 111 001...

Page 88: ...ter Condition Codes x N z v c X Cleared if bit 4 of immediate operand is zero Unchanged otherwise N Cleared if bit 3 of immediate operand is zero Unchanged otherwise Z Cleared if bit 2 of immediate operand is zero Unchanged otherwise V Cleared if bit 1 of immediate operand is zero Unchanged otherwise C Cleared if bit 0 of immediate operand is zero Unchanged otherwise Instruction Format 15 14 13 12...

Page 89: ...ted bits of the status register are affected Condition Codes x N z v c X Cleared if bit 4 of immediate operand is zero Unchanged otherwise N Cleared if bit 3 of immediate operand is zero Unchanged otherwise Z Cleared if bit 2 of immediate operand is zero Unchanged otherwise V Cleared if bit 1 of immediate operand is zero Unchanged otherwise C Cleared if bit 0 of immediate operand is zero Unchanged...

Page 90: ...ster specified by the instruction modulo 64 An operand in memory can be shifted one bit only and the operand size is restricted to a word For ASL the operand is shifted left the number of positions shifted is the shift count Bits shifted out of the high order bit go to both the carry and the extend bits zeros are shifted into the low order bit The overflow bit indicates if any sign changes occur d...

Page 91: ...GISTER dr SIZE ilr o 0 REGISTER Instruction Fields Register Shifts CounVRegister field Specifies shift count or register that contains shift count If i r 0 this field contains the shift count The values one to seven represent counts of one to seven value of zero represents a count of eight If i r 1 this field specifies the data register that contains the shift count modulo 64 dr field Specifies th...

Page 92: ...Shift left Effective Address field Specifies the operand to be shifted Only memory alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode On xxx w An xxx L An 010 Reg number An data An 011 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC dS An Xn 110 Reg number An dS PC Xn bd An Xn 110 Reg number An bd PC Xn CPU32 REFERENCE MANUAL INSTRUCTIO...

Page 93: ...ement field in the instruction word is all ones FF the 32 bit displacement long word immediately following the instruction is used Condition codes are specified as follows cc Name Code Description cc Name Code Description CC Carry Clear 0100 C LS Low or Same 0011 C Z CS Carry Set 0101 C LT Less Than 1101 N V N V EQ Equal 0111 Z MI Minus 1011 N GE Greater or Equal 1100 N V N V NE Not Equal 0110 Z G...

Page 94: ...next instruction to be executed if the condition is met 16 Bit Displacement field Used for displacement when 8 bitdisplacement field contains OO 32 Bit Displacement field Used for displacement when 8 bit displacement field contains FF NOTE A branch to the instruction immediately following automatically uses 16 bit displacement because the 8 bit displacement field contains 00 zero offset CPU32 REFE...

Page 95: ...a byte operation and the bit number is modulo 8 In all cases bit zero refers to the least significant bit The bit number for this operation may be specified in either of two ways 1 Immediate The bit number is specified by a second instruction word 2 Register The specified data register contains the bit number Condition Codes X N X Not affected N Not affected z v C Z Set if the bit tested is zero C...

Page 96: ...ruction Format Bit Number Dynamic specified in a register 15 14 13 12 11 10 9 a 7 6 5 4 3 2 o EFFECTIVE ADDRESS 0 0 0 0 REGISTER 1 0 1 I MODE REGISTER Instruction Fields Bit Number Dynamic Register field Specifies the data register that contains the bit number Effective Address field Specifies the destination location Only data alterable addressing modes are allowed as shown Addressing Mode Mode R...

Page 97: ...on and the bit number is modulo 8 In al cases bit zero refers to the least significant bit The bit number for this operation can be specified in either of two ways 1 Immediate The bit number is specified by a second instruction word 2 Register The specified data register contains the bit number Condition Codes X N X Not affected N Not affected z v C Z Set if the bit tested is zero Cleared otherwis...

Page 98: ...uction Format Bit Number Dynamic specified in a register 15 14 13 12 11 10 9 a 7 6 5 4 3 2 o EFFECTIVE ADDRESS 0 a 0 0 REGISTER 1 1 0 I MODE REGISTER Instruction Fields Bit Number Dynamic Register field Specifies the data register that contains the bit number Effective Address field Specifies the destination location Only data alterable addressing modes are allowed as shown Addressing Mode Mode Re...

Page 99: ...ckground mode instruction execution continues with the instruction pointed to by the program counter If background mode is not enabled the processor initiates illegal instruction exception processing The vector number is generated to reference the illegal instruction exception vector Background mode is covered in SECTION 7 DEVELOPMENT SUPPORT Condition Codes x N X Not affected N Not affected Z Not...

Page 100: ...eakpoint instruction requires a word transfer if the first bus cycle accesses an 8 bit port a second cycle is required If III external logic terminates the breakpoint acknowledge cycle with BERR Le no instruction word available the processor takes an illegal instruction exception Refer to 7 2 5 Software Breakpoints for details of breakpoint operation This instruction supports breakpoints for debug...

Page 101: ... word immediately following the instruction is used Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o o I 1 I 1 I o I o I o I o I o I 8 BIT DISPLACEMENT 16 BIT DISPLACEMENT IF 8 BIT DISPLACEMENT 00 32 BIT DISPLACEMENT IF 8 BIT DISPLACEMENT FF Instruction Fields 8 Bit Displacement field Twos complement integer specifying the number of bytes between the branch instr...

Page 102: ...operation and the bit number is modulo 8 In all cases bit zero refers to the least significant bit The bit number for this operation can be specified in two ways 1 Immediate The bit number is specified by the second word of the instruction 2 Register The specified data register contains the bit number Condition Codes X N X Not affected N Not affected Z v C Z Set if the bit tested is zero Cleared o...

Page 103: ...ruction Format Bit Number Dynamic specified In a register 15 14 13 12 11 10 9 a 7 6 5 4 3 2 EFFECTIVE ADDRESS 0 0 0 0 REGISTER 1 1 1 I MODE REGISTER Instruction Fields Bit Number Dynamic Register field Specifies the data register that contains the bit number Effective Address field Specifies the destination location Only data alterable addressing modes are allowed as shown Addressing Mode Mode Reg...

Page 104: ...nstruction word is all ones FF the 32 bit displacement long word immediately following the instruction is used Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o 0 I 1 I 1 I o I o I o I o I 1 I 8 BIT DISPLACEMENT 16 BIT DISPLACEMENT IF 8 BIT DISPLACEMENT 00 32 BIT DISPLACEMENT IF 8 BIT DISPLACEMENT FF Instruction Fields 8 Bit Displacement field Twos complement inte...

Page 105: ...all cases bit zero refers to the least significant bit The bit number for this operation can be specified in either of two ways 1 Immediate The bit number is specified by a second word of the instruction 2 Register The specified data register contains the bit number Condition Codes x N X Not affected N Not affected z v C Z Set if the bit tested is zero Cleared otherwise V Not affected C Not affect...

Page 106: ...rmat Bit Number Dynamic specified in a register 15 14 13 12 11 10 9 9 7 6 5 4 3 2 o EFFECTIVE ADDRESS 0 0 0 0 REGISTER 1 0 0 I MODE REGISTER Instruction Fields Bit Number Dynamic Register field Specifies the data register that contains the bit number Effective Address field Specifies the destination location Only data addressing modes are allowed as shown Addressing Mode Mode Register Addressing M...

Page 107: ...umber 6 occurs Condition Codes x N Z v c u u u X Not affected N Set if On 0 cleared if On effective address operand Undefined otherwise Z Undefined V Undefined C Undefined Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 EFFECTIVr ADDRESS 0 1 0 0 REGISTER SIZE 0 MODE REGISTER Instruction Fields Register field Specifies the data register that contains the value to be checked Size field Specifie...

Page 108: ...ter Addressing Mode On 000 Reg number On xxx W An xxx L An 010 Reg number An data An 011 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC dS An Xn 110 Reg number An ds PC Xn bd An Xn 110 Reg number An bd PC Xn Long only all others are byte only CPU32 REFERENCE MANUAL INSTRUCTION SET Mode 111 111 111 111 111 Register 000 001 010 011 011 MOTOROLA 4 55 III ...

Page 109: ...r long If Rn is a data register and the operation size is byte or word only the appropriate low order part of Rn is checked If Rn is an address register and the operation size is byte or word the bounds operands are sign extended to 32 bits and the resultant operands are compared to the full 32 bits of An If the upper bound equals the lower bound the valid range is a single value If the register v...

Page 110: ...rands Only control addressing modes are allowed as shown Addressing Mode Mode Reg ister Addressing Mode Mode Dn xxx w 111 An xxx L 111 An 010 Reg number An data An An d16 An 101 Reg number An d16 PC 111 dS An Xn 110 Reg number An d8 PC Xn 111 bd An Xn 110 Reg number An bd PC Xn 111 D A field Specifies whether an address register or data register is to be checked o Data register 1 Address register ...

Page 111: ...Z V C o 0 0 X Not affected N Always cleared Z Always set V Always cleared C Always cleared Instruction Format 15 14 13 12 11 10 9 8 0 1 0 0 0 0 1 0 Instruction Fields Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation 7 SIZE MOTOROLA 4 58 INSTRUCTION SET CLR 6 5 4 3 2 o EFFECTIVE ADDRESS MODE I REGISTER CPU32 REFERENCE MANUAL ...

Page 112: ...n Addressing Mode Mode Dn 000 An An 010 An 011 An 100 d16 An 101 de An Xn 110 bd An Xn 110 CPU32 REFERENCE MANUAL Register Addressing Mode Reg Number Dn xxx W xxx L Reg number An data Reg number An Reg number An Reg number An d16 PC Reg number An de PC Xn Reg number An bd PC Xn INSTRUCTION SET Mode 111 111 Register 000 001 MOTOROLA 4 59 III ...

Page 113: ...X Not affected N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if an overflow occurs Cleared otherwise C Set if a borrow occurs Cleared otherwise Instruction Format 15 14 13 12 11 10 9 8 7 1 0 1 1 REGISTER OPMODE Instruction Fields Register field Specifies the destination data register Opmode field 6 Byte 000 Word 001 Long 010 Operation Dn ea M...

Page 114: ... data 111 100 An Q11 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC 111 010 d8 An Xn 110 Reg number An d8 PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 Word and long only NOTE CMPA is used when the destination is an address register CMPI is used when the source is immediate data CMPM is used for memory to memory compares Most assemblers automatically make the distin...

Page 115: ...d N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if an overflow is generated Cleared otherwise C Set if a borrow is generated Cleared otherwise Instruction Format 15 14 13 12 11 10 9 8 7 1 0 1 1 REGISTER OPMODE Instruction Fields 6 Register field Specifies the destination address register Opmode field Specifies the size of the operation 5 4 3 ...

Page 116: ...n 010 An 011 An 100 d16 An 101 d8 An Xn 110 bd An Xn 110 CPU32 REFERENCE MANUAL Register Addressing Mode Reg number Dn xxx w Reg number An xxx L Reg number An data Reg number An Reg number An Reg number An d16 PC Reg number An d8 PC Xn Reg number An bd PC Xn INSTRUCTION SET Mode 111 111 111 111 111 111 Register 000 001 100 010 011 011 MOTOROLA 4 63 III ...

Page 117: ...ition Codes x N Z v C X Not affected N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if an overflow occurs Cleared otherwise C Set if a borrow occurs Cleared otherwise Instruction Format 15 14 13 12 11 10 9 8 0 0 0 0 1 1 0 0 WORD DATA 16 BITS 7 6 SIZE LONG DATA 32 BITS Instruction Fields Size field Specifies the size of the operation 00 Byte op...

Page 118: ...eg number An An 100 Reg number An d16 An 101 Reg number An d16 PC da An Xn 110 Reg number An da PC Xn bd An Xn 110 Reg number An bd PC Xn Immediate field Data immediately following the instruction If size 00 the data is the low order byte of the immediate word If size 01 the data is the entire immediate word If size 10 the data is the next two immediate words CPU32 REFERENCE MANUAL INSTRUCTION SET...

Page 119: ...the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if an overflow is generated Cleared otherwise C Set if a borrow is generated Cleared otherwise Instruction Format 15 14 13 12 11 10 9 8 7 6 o REGISTER Ax SIZE Instruction Fields 5 4 3 2 0 o I 0 I REGISTERAy Register Ax field always the destination Specifies an address register in the postincrement addressi...

Page 120: ... appropriate low order part of Rn is checked If Rn is an address register and the operation size is byte or word the bounds operands are sign extended to 32 bits and the resultant operands are compared to the full 32 bits of An If the upper bound equals the lower bound the valid range is a single value NOTE This instruction is identical to CHK2 except that it sets condition codes rather than takin...

Page 121: ...e Mode Register Addressing Mode Mode Dn xxx w 111 An xxx L 111 An 010 Reg number An data An An d16 An 101 Reg number An d16 PC 111 dS An Xn 110 Reg number An d8 PC Xn 111 bd An Xn 110 Reg number An bd PC Xn 111 D A field Specifies whether an address register or data register is compared o Data register 1 Address register Register 000 001 010 011 011 Register field Specifies the address or data reg...

Page 122: ...he current value of the PC plus the sign extended 16 bit displacement The value in the PC is the address of the instruction word of the OBcc instruction plus two The displacement is a twos complement integer that represents the relative distance in bytes from the current PC to the destination PC Condition code cc specifies one of the following conditions cc Name Code Description cc Name CC Carry C...

Page 123: ...minus 2 Most assemblers accept DSRA for DSF when a count terminates the loop no condition is tested 3 A program can enter a loop at the beginning or by branching to the trailing DScc instruction Entering the loop at the beginning is useful for indexed addressing modes and dynamically specified bit operations In this case the control index count must be one less than the desired number of loop exec...

Page 124: ...idend lower word least significant 16 bits and a remainder in the upper word most significant 16 bits of III The first long form divides a long word by a long word The result is a long quotient the remainder is discarded The second long form divides a quad word in any two data registers by a long word The result is a long word quotient and a long word remainder The third long form divides a long w...

Page 125: ...DE REGISTER Instruction Fields Register field Specifies any of the eight data registers This field always specifies the destination operand Effective Address field Specifies the source operand Only data addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg nu...

Page 126: ... number An dg PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 Register Dq field Specifies a data register for the destination operand The low order 32 bits of the dividend come from this register and the 32 bit quotient is loaded into this register Size field Selects a 32 or 64 bit division operation 0 32 bit dividend is in Register Dq 1 64 bit dividend is in Dr Dq Register Dr field Afte...

Page 127: ... remainder is discarded The second long form divides a quad word in any two data registers by a long word The result is a long word quotient and a long word remainder The third long form divides a long word by a long word The result is a long word quotient and a long word remainder Two special conditions may arise during the operation 1 Division by zero causes a trap 2 Overflow may be detected bef...

Page 128: ...ies the source operand Only data addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode On 000 Reg number On xxx w 111 An xxx L 111 An 010 Reg number An data 111 An 011 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC 111 de An Xn 110 Reg number An de PC Xn 111 bd An Xn 110 Reg number An bd PC Xn 111 NOTE Overflow occurs if the quotient is larger...

Page 129: ...110 Reg number An de PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 Register Dq field Specifies a data register for the destination operand The low order 32 bits of the dividend come from this register and the 32 bit quotient is loaded into this register Size field Selects a 32 or 64 bit division operation o 32 bit dividend is in Register Dq 1 64 bit dividend is in Dr Dq Register Dr fie...

Page 130: ...pecified in the effective address field Condition Codes x N z v C o 0 X Not affected N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result is zero Cleared otherwise V Always cleared C Always cleared Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o EFFECTIVE ADDRESS 1 0 1 1 REGISTER OPMODE Instruction Fields Register field Specifies any of the eight data...

Page 131: ...ister MOTOROLA 4 78 On 000 Reg number On xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC ds An Xn 110 Reg number An dS PC Xn bd An Xn 110 Reg number An bd PC Xn NOTE Memory to data register operations are not allowed Most assemblers use EaRl when the source is immediate data INSTRUCTION SET CPU32 REFERENCE MANUAL ...

Page 132: ...t match the operation size Condition Codes x N Z v C o 0 X Not affected N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result is zero Cleared otherwise V Always cleared C Always cleared Instruction Format 15 14 13 12 11 10 9 8 7 6 o o o o o o SIZE WORD DATA 16 BITS LONG DATA 32 BITS Instruction Fields Size field Specifies the size of the operation 00 Byte ope...

Page 133: ...n data An 011 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC de An Xn 110 Reg number An de PC Xn bd An Xn 110 Reg number An bd PC Xn Immediate field Data immediately following the instruction If size 00 the data is the low order byte of the immediate word If size 01 the data is the entire immediate word If size 10 the data is next two immediate words Mode Register 111 000 111 0...

Page 134: ...er All implemented bits of the condition code register are affected Condition Codes x N z v c X Changed if bit 4 of immediate operand is one Unchanged otherwise N Changed if bit 3 of immediate operand is one Unchanged otherwise Z Changed if bit 2 of immediate operand is one Unchanged otherwise V Changed if bit 1 of immediate operand is one Unchanged otherwise C Changed if bit 0 of immediate operan...

Page 135: ...mented bits of the status register are affected Condition Codes x N z v c X Changed if bit 4 of immediate operand is one Unchanged otherwise N Changed if bit 3 of immediate operand is one Unchanged otherwise Z Changed if bit 2 of immediate operand is one Unchanged otherwise V Changed if bit 1 of immediate operand is one Unchanged otherwise C Changed if bit 0 of immediate operand is one Unchanged o...

Page 136: ...ISTER Rx OPMODE REGISTER Ry Instruction Fields Register Rx field Specifies either a data register or an address register depending on the mode If the exchange is between data and address registers this field always specifies the data register Opmode field Specifies the type of exchange 01000 Data registers 01001 Address registers 10001 Data register and address register Register Ry field Specifies...

Page 137: ...register is copied to bits 31 16 of the data register The EXTB form copies bit 7 of the designated register to bits 31 8 of the data register Condition Codes x N z v c o 0 X Not affected N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Always cleared C Always cleared Instruction Format 15 14 13 12 11 10 9 8 7 6 o 1 0 0 o I 0 OPMODE Instruction Field...

Page 138: ... Unsized ILLEGAL Description Forces an illegal instruction exception vector number 4 All other illegal instruction bit patterns are reserved for future extension of the instruction set and should not be used to force an exception Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 o o I CPU32 REFERENCE MANUAL INSTRUCTION SET 6 5 4 3 2 o o I 0 I MOTOROLA 4 85 III ...

Page 139: ...2 11 10 9 8 7 6 5 4 3 2 o EFFECTIVE ADDRESS 0 1 0 0 1 1 1 0 1 1 I MODE REGISTER Instruction Fields Effective Address field Specifies the address of the next instruction Only control addressing modes are allowed as shown Addressing Mode MOTOROLA 4 86 Dn An An An An d16 An dS An Xn bd An Xn Mode 010 101 110 110 Register Addressing Mode Mode Register xxx w 111 000 xxx L 111 001 Reg number An data Reg...

Page 140: ...truction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o EFFECT11ADDRESS 0 1 0 0 1 1 1 0 1 0 MODE REGISTER Instruction Fields Effective Address field Specifies the address of the next instruction Only control addressing modes are allowed as shown Addressing Mode Mode Dn An An 010 An An d16 An 101 d8 An Xn 110 bd An Xn 110 CPU32 REFERENCE MANUAL Register Addressing Mode xxx W xxx L Reg number An data Re...

Page 141: ... 1 I MODE REGISTER Instruction Fields Register field Specifies the address register to be updated with the effective address Effective Address field Specifies the address to be loaded into the address register Only control addressing modes are allowed as shown Addressing Mode MOTOROLA 4 88 Dn An An An An d16 An d8 An Xn bd An Xn Mode 010 101 110 110 Register Addressing Mode Mode Register xxx w 111...

Page 142: ...on word The address register occupies one long word on the stack The user should specify a negative displacement to allocate stack area Condition Codes Not affected Instruction Format 15 14 13 12 9 8 7 5 4 3 2 1 0 REGISTER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 o 1 1 1 0 1 0 1 1 1 0101010101010111 REGISTER HIGH ORDER DISPLACEMENT LOW ORDER DISPLACEMENT Instruction Fields Register field Specifies the ...

Page 143: ...a trace interrupt or reset exception occurs A trace exception occurs if the trace state is on when the LPSTOP instruction is executed If an interrupt request is asserted with a higher priority that the current priority level set by the new status register value an interrupt exception occurs otherwise the interrupt request is ignored If the bit of the immediate data corresponding to the S bit is of...

Page 144: ...ze of the operation for register destinations may be specified as byte word or long The III contents of memory ea can be shifted one bit only and the operand size is restricted to a word The LSL instruction shifts the operand to the left the number of positions specified as the shift count Bits shifted out of the high order bit go to both the carry and the extend bits zeros are shifted into the lo...

Page 145: ...egister Shifts Count Register field Specifies shift count or register that contains shift count If i r 0 this field contains the shift count The values one to seven represent counts of one to seven value of zero represents a count of eight If i r 1 this field specifies the data register that contains the shift count modulo 64 dr field Specifies the direction of the shift Shift right 1 Shift left S...

Page 146: ...hift left Effective Address field Specifies the operand to be shifted Only memory alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Dn xxx W An xxx L An 010 Reg number An data An 011 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC dS An Xn 110 Reg number An d8 PC Xn bd An Xn 110 Reg number An bd PC Xn CPU32 REFERENCE MANUAL INSTRUCTION...

Page 147: ...odes x N Z v c o 0 X Not affected N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Always cleared C Always cleared Instruction Format 15 14 13 12 11 10 9 8 DESTINATION 0 0 SIZE 7 REGISTER I MODE Instruction Fields 6 Size field Specifies the size of the operand to be moved 01 Byte operation 11 Word operation 10 Long operation MOTOROLA 4 94 INSTRUCTIO...

Page 148: ...ss field Specifies the source operand All addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode On 000 Reg number On xxx w 111 An 001 Reg number An xxx L 111 An 010 Reg number An data 111 An 011 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC 111 dB An Xn 110 Reg number An dB PC Xn 111 bd An Xn 110 Reg number An bd PC Xn 111 For byte size opera...

Page 149: ...e moved 11 Word operation The source operand is sign extended to a long operand and all 32 bits are loaded into the address register 10 Long operation Destination Register Dst Reg field Specifies the destination address register Effective Address field Specifies the location of the source operand All addressing modes are allowed as shown Addressing Mode MOTOROLA 4 96 Dn An An An An d16 An de An Xn...

Page 150: ...0 0 1 a 1 1 I MODE REGISTER Instruction Fields Effective Address field Specifies the destination location Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC dS An Xn 110 Reg number ...

Page 151: ...byte of the status register is not altered Condition Codes x N z v C X Set to the value of bit 4 of the source operand N Set to the value of bit 3 of the source operand Z Set to the value of bit 2 of the source operand V Set to the value of bit 1 of the source operand C Set to the value of bit 0 of the source operand Instruction Format 15 14 13 12 11 10 9 8 0 1 0 0 0 1 0 0 7 1 MOTOROLA 4 98 INSTRU...

Page 152: ...ssing Mode Mode Register On 000 Reg number On xxx w 111 000 An xxx L 111 001 An 010 Reg number An data 111 100 An 011 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC 111 010 ds An Xn 110 Reg number An ds PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 NOTE MOVE to CCR is a word operation ANDI ORI and EORI to CCR are byte operations CPU32 REFERENCE MANUAL INSTRUCTION SE...

Page 153: ...7 6 5 4 3 2 o EFFECTIVE ADDRESS 0 1 0 0 0 0 0 0 1 1 I MODE REGISTER Instruction Fields Effective Address field Specifies the destination location Only data alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx w 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An d16 An 101 Reg n...

Page 154: ...ion Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o EFFECTIVE ADDRESS 0 1 0 0 0 1 1 0 1 1 I MODE REGISTER Instruction Fields Effective Address field Specifies the destination location Only data addressing modes are allowed as shown Addressing Mode Mode Dn 000 An An 010 An 011 An 100 d16 An 101 ds An Xn 110 bd An Xn 110 CPU32 REFERENCE MANUAL Register Addressing Mode Reg number Dn xxx w xxx L Reg number...

Page 155: ... to or from the specified address register Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 0 I 1 I 0 I 0 I 1 I 1 1 I 0 I Instruction Fields dr field Specifies the direction of transfer o Transfer the address register to the USP 1 Transfer the USP to the address register 7 6 5 4 3 2 0 0 I 1 1 I 0 I dr REGISTER Register field Specifies the address register for the operation MOT...

Page 156: ...ented bits are read as zeros Condition Codes Not affected Instruction Format 14 13 12 10 8 Instruction Fields dr field Specifies the direction of the transfer 0 Control register to general register 1 General register to control register AID field Specifies the type of general register o Data register 1 Address register 7 Register field Specifies the register number Control Register field Specifies...

Page 157: ... data register 7 then from address register 0 to address register 7 If the effective address is specified by the predecrement mode only a register to memory operation is allowed The registers are stored starting at the specified address minus the operand length 2 or 4 and the address is decremented by the operand length following each transfer The order of storing is from address register 7 to add...

Page 158: ...being transferred 4 o Word transfer 1 Long transfer Effective Address field Specifies the memory address for the operation For register to memory transfers only control alterable addressing modes or the predecrement addressing mode are allowed as shown Addressing Mode Mode Dn An An 010 An An 100 d16 An 101 de An Xn 110 bd An Xn 110 CPU32 REFERENCE MANUAL Register Addressing Mode xxx w xxx L Reg nu...

Page 159: ...ferred The low order bit corresponds to the first register to be transferred the high order bit corresponds to the last register to be transferred Thus both for control modes and for the postincrement mode addresses the mask correspondence is 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o I A7 I A6 I A5 I A4 I A3 I A2 I A1 I AO I 07 06 05 04 03 02 01 DO For predecrement mode addresses the mask correspondence...

Page 160: ...byte is transferred last The memory address is specified by the address register indirect plus 16 bit displacement addressing mode If the address is even all the transfers are to or from the high order half of the data bus if the address is odd all the transfers are to or from the low order half of the data bus The instruction also accesses alternate bytes on an 8 or 32 bit bus Example Long transf...

Page 161: ...the data register for the instruction Opmode field Specifies the direction and size of the operation 100 Transfer word from memory to register 101 Transfer long from memory to register 110 Transfer word from register to memory 111 Transfer long from register to memory o 4 MOVEP 7 o LOW ORDER 3 2 0 ADDR REGISTER Address Register field Specifies the address register which is used in the address regi...

Page 162: ...ter as it is transferred Condition Codes x N z v c o 0 X Not affected N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Always cleared C Always cleared Instruction Format 15 14 13 12 11 10 9 8 7 o I 1 1 1 REGISTER o I Instruction Fields Register field Specifies the data register to be loaded 6 5 4 3 DATA Data field Eight bits of data which are sign e...

Page 163: ...n code SFC register to the specified general register If the destination is a data register the source operand replaces the corresponding low order bits of the data register depending on the size of the operation If the destination is an address register the source operand is sign extended to 32 bits and then loaded into the address register Condition Codes Not affected Instruction Format 15 14 13...

Page 164: ... general register o Data register 1 Address register Register field Specifies the register number dr field Specifies the direction of the transfer o From ea to general register 1 From general register to ea AddressIng Mode xxx w xxx L data d16 PC ds PC Xn bd PC Xn NOTE Mode Register 111 000 111 001 For either of the two following examples which use the same address register as both source and dest...

Page 165: ...ster In the long form the multiplier and multiplicand are both long word operands and the result is either a long word or a quad word The long word result is the low order 32 bits of the quad word result the high order 32 bits of the product are discarded Condition Codes x N z v c o X Not affected N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set...

Page 166: ...d Specifies the source operand Only data addressing modes are allowed as shown Addressing Mode Mode Dn 000 An An 010 An 011 An 100 d16 An 101 ds An Xn 110 bd An Xn 110 CPU32 REFERENCE MANUAL Register Addressing Mode Reg number Dn xxx W xxx L Reg number An data Reg number An Reg number An Reg number An d16 PC Reg number An dS PC Xn Reg number An bd PC Xn INSTRUCTION SET Mode 111 111 111 111 111 111...

Page 167: ...01 Reg number An d16 PC 111 010 ds An Xn 110 Reg number An ds PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 Register 01 field Specifies a data register for the destination operand The 32 bit multiplicand comes from this register and the low order 32 bits of the product are loaded into this register Size field Selects a 32 or 64 bit product o 32 bit product to be returned to register 01...

Page 168: ...n data register In the long form the multiplier and multiplicand are both long word operands and the result is either a long word or a quad word The long word result is the low order 32 bits of the quad word III result the high order 32 bits of the product are discarded Condition Codes x N z v c o X Not affected N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared ...

Page 169: ...field Specifies the source operand Only data addressing modes are allowed as shown Addressing Mode MOTOROLA 4 116 On An An An An d16 An dg An Xn bd An Xn Mode 000 010 011 100 101 110 110 Register Addressing Mode Mode Register Reg number On xxx W 111 000 xxx L 111 001 Reg number An data 111 100 Reg number An Reg number An Reg number An d16 PC 111 010 Reg number An dg PC Xn 111 011 Reg number An bd ...

Page 170: ...ber An d16 An 101 Reg number An d16 PC 111 010 dS An Xn 110 Reg number An ds PC Xn 111 011 bd An Xn 110 Reg number An bd PC Xn 111 011 Register 01 field Specifies a data register for the destination operand The 32 bit multiplicand comes from this register and the low order 32 bits of the product are loaded into this register Size field Selects a 32 or 64 bit product 0 32 bit product to be returned...

Page 171: ...it is zero or the nines complement if the extend bit is one Condition Codes X N z v u u X Set the same as the carry bit N Undefined C Z Cleared if the result is non zero Unchanged otherwise V Undefined C Set if a decimal borrow occurs Cleared otherwise NOTE Normally the Z condition code bit is set via programming before the start of the operation This allows successful tests for zero results upon ...

Page 172: ...llowed as shown Addressing Mode Mode Dn 000 An An 010 An 011 An 100 d16 An 101 de An Xn 110 bd An Xn 110 CPU32 REFERENCE MANUAL Register Addressing Mode Reg number Dn xxx w xxx L Reg number An data Reg number An Reg number An Reg number An d16 PC Reg number An de PC Xn Reg number An bd PC Xn INSTRUCTION SET Mode 111 111 Register 000 001 MOTOROLA 4 119 III ...

Page 173: ...N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if an overflow occurs Cleared otherwise C Cleared if the result is zero Set otherwise Instruction Format 15 14 13 12 11 10 9 8 0 1 0 0 0 1 0 0 Instruction Fields Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation 7 SIZE MOTOROLA 4 120 INSTRUCTION S...

Page 174: ...ssing Mode Mode Dn 000 An An 010 An 011 An 100 d16 An 101 de An Xn 110 bd An Xn 110 CPU32 REFERENCE MANUAL Reg ister Addressing Mode Reg number Dn xxx w xxx L Reg number An data Reg number An Reg number An Reg number An d16 PC Reg number An de PC Xn Reg number An bd PC Xn INSTRUCTION SET Mode 111 111 Register 000 001 MOTOROLA 4 121 III ...

Page 175: ...ro Cleared otherwise V Set if an overflow occurs Cleared otherwise C Cleared if the result is zero Set otherwise NOTE Normally the Z condition bit is set via programming before the start of the operation This allows successful tests for zero results upon completion of multiple preCision operations Instruction Format 15 14 13 12 11 10 9 8 0 1 0 0 0 0 0 0 Instruction Fields Size field Specifies the ...

Page 176: ...wn Addressing Mode Mode Dn 000 An An 010 An 011 An 100 d16 An 101 de An Xn 110 bd An Xn 110 CPU32 REFERENCE MANUAL Register Addressing Mode Reg number Dn xxx W xxx L Reg number An data Reg number An Reg number An Reg number An d16 PC Reg number An de PC Xn Reg number An bd PC Xn INSTRUCTION SET Mode 111 111 Register 000 001 MOTOROLA 4 123 III ...

Page 177: ...ution continues with the instruction following the NOP instruction The NOP instruction does not begin execution until all pending bus cycles are completed This synchronizes the pipeline and prevents instruction overlap Condition Codes Not affected Instruction 15 0 MOTOROLA 4 124 I Format 14 13 0 12 11 I 0 I 10 9 8 7 6 5 4 3 2 o 1 I 0 I 0 I 1 o I 0 I 0 I 1 I INSTRUCTION SET CPU32 REFERENCE MANUAL ...

Page 178: ...des x N Z v C o 0 X Not affected N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Always cleared C Always cleared Instruction Format 15 14 13 12 11 10 9 8 0 1 0 0 0 1 1 0 Instruction Fields Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation 7 SIZE CPU32 REFERENCE MANUAL INSTRUCTION SET 6 5 4 3 2 o EF...

Page 179: ...own Addressing Mode MOTOROLA 4 126 On An An An An d16 An ds An Xn bd An Xn Mode 000 010 011 100 101 110 110 Register Addressing Mode Mode Register Reg number On xxx w 111 000 xxx L 111 001 Reg number An data Reg number An Reg number An Reg number An d16 PC Reg number An ds PC Xn Reg number An bd PC Xn INSTRUCTION SET CPU32 REFERENCE MANUAL ...

Page 180: ... an operand Condition Codes x N z v C a a X Not affected N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result is zero Cleared otherwise V Always cleared C Always cleared Instruction Format 15 14 13 12 11 10 9 8 7 6 5 1 1 0 0 REGISTER OPMODE Instruction Fields Register field Specifies any of the eight data registers Opmode field Byte 000 100 CPU32 REFERENCE M...

Page 181: ...ber An bd PC Xn 111 011 If the location specified is a destination operand only memory alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register On xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC de An Xn 110 Reg number An de PC Xn bd An Xn 110 Reg number An bd PC Xn...

Page 182: ... size Condition Codes x N Z v C o 0 X Not affected N Set if the most significant bit of the result is set Cleared otherwise Z Set if the result is zero Cleared otherwise V Always cleared C Always cleared Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o EFFECTIVE ADDRESS 0 0 0 0 a 0 0 0 SIZE WORD DATA 16 BITS LONG DATA 32 BITS Instruction Fields Size field Specifies the size of the operation ...

Page 183: ...ta An 011 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC de An Xn 110 Reg number An de PC Xn bd An Xn 110 Reg number An bd PC Xn Immediate field Data immediately following the instruction If size 00 the data is the low order byte of the immediate word If size 01 the data is the entire immediate word If size 10 the data is the next two immediate words Mode Register 111 000 111 0...

Page 184: ...l implemented bits of the condition code register are affected Condition Codes x N z v c X Set if bit 4 of immediate operand is zero Unchanged otherwise N Set if bit 3 of immediate operand is zero Unchanged otherwise Z Set if bit 2 of immediate operand is zero Unchanged otherwise V Set if bit 1 of immediate operand is zero Unchanged otherwise C Set if bit 0 of immediate operand is zero Unchanged o...

Page 185: ...ll implemented bits of the status register are affected Condition Codes x N z v c X Set if bit 4 of immediate operand is zero Unchanged otherwise N Set if bit 3 of immediate operand is zero Unchanged otherwise Z Set if bit 2 of immediate operand is zero Unchanged otherwise V Set if bit 1 of immediate operand is zero Unchanged otherwise C Set if bit aof immediate operand is zero Unchanged otherwise...

Page 186: ...FFECTIVE ADDRESS 0 1 0 0 1 0 0 0 0 1 I MODE REGISTER Instruction Fields Effective Address field Specifies the address to be pushed onto the stack Only control addressing modes are allowed as shown Addressing Mode Mode On An An 010 An An d16 An 101 dS An Xn 110 bd An Xn 110 CPU32 REFERENCE MANUAL Register Addressing Mode xxx W xxx L Reg number An data Reg number An d16 PC Reg number An ds PC Xn Reg...

Page 187: ...sserts the RESET signal for 512 clock periods resetting all external devices The processor state other than the program counter is unaffected and execution continues with the next instruction Condition Codes Not affected Instruction 15 0 MOTOROLA 4 134 I Format 14 13 0 12 I 0 11 10 9 8 7 I 1 I 1 I 0 I 0 I INSTRUCTION SET 6 5 4 3 2 0 1 I 1 I 0 I 0 I 0 I 0 I CPU32 REFERENCE MANUAL ...

Page 188: ...ion modulo 64 contents of memory ea can be rotated one bit only and operand size is restricted to a word The size of the operation for register destinations is specified as byte word or long The III The ROL instruction rotates the bits of the operand to the left the rotate count determines the number of bit positions rotated Bits rotated out of the high order bit go to the carry bit and also back ...

Page 189: ...e rotate count The values 1 7 represent counts of 1 7 and 0 specifies a count of 8 If i r 1 this field specifies a data register that contains the rotate count modulo 64 dr field Specifies the direction of the rotate o Rotate right 1 Rotate left Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation i r field Specifies the rotate count location If i r ...

Page 190: ... MODE I REGISTER Effective Address field Specifies the operand to be rotated Only memory alterable addressing modes are allowed as shown Addressing Mode Mode On An An 010 An 011 An 100 d16 An 101 de An Xn 110 bd An Xn 110 CPU32 REFERENCE MANUAL Register Addressing Mode xxx w xxx L Reg number An data Reg number An Reg number An Reg number An d16 PC Reg number An de PC Xn Reg number An bd PC Xn INST...

Page 191: ...for register destinations is specified as byte word or long The contents of memory ea can be rotated one bit only and operand size is restricted to a word The ROXL instruction rotates the bits of the operand to the left the rotate count determines the number of bit positions rotated Bits rotated out of the high order bit go to the carry bit and the extend bit the previous value of the extend bit r...

Page 192: ...NTIREGISTERI dr SIZE i r o I REGISTER Instruction Fields Register Rotate Count Register field If i r 0 this field contains the rotate count The values 1 7 represent counts of 1 7 and 0 specifies a count of 8 If ilr 1 this field specifies a data register that contains the rotate count modulo 64 dr field Specifies the direction of the rotate 0 Rotate right 1 Rotate left Size field Specifies the size...

Page 193: ... 1 I MODE REGISTER Effective Address field Specifies the operand to be rotated Only memory alterable addressing modes are allowed as shown Addressing Mode MOTOROLA 4 140 Dn An An An An d16 An de An Xn bd An Xn Mode 010 011 100 101 110 110 Register Addressing Mode Mode Register xxx W 111 000 xxx L 111 001 Reg number An data Reg number An Reg number An Reg number An d16 PC Reg number An de PC Xn Reg...

Page 194: ...dds the sign extended 16 bit displacement value to the stack pointer The previous program counter value is lost ConditIon Codes Not affected Instruction Format 15 14 13 12 10 9 8 7 6 4 3 2 o Instruction Field Displacement field Specifies the twos complement integer to be sign extended and added to the stack pointer CPU32 REFERENCE MANUAL INSTRUCTION SET MOTOROLA 4 141 III ...

Page 195: ...rd Contains the format code which implies the stack frame size including the format offset word 0000 Short Format removes four words Loads the status register and the program counter from the stack frame 0001 Throwaway Format removes four words Loads the status register from the stack frame and switches to the active system stack Continues the instruction using the active system stack 0010 Instruc...

Page 196: ...rogram counter values from the stack The previous condition codes and program counter values are lost The supervisor portion of the status register is unaffected Condition Codes Set to the condition codes from the stack Instruction Format 15 14 13 12 11 10 9 8 7 6 o I 0 I 0 I 1 1 o I 0 I 1 CPU32 REFERENCE MANUAL INSTRUCTION SET 5 4 3 2 o o I 1 I MOTOROLA 4 143 III ...

Page 197: ...utes Unsized Description Pulls the program counter value from the stack The previous value is lost Condition Codes Not affected Instruction 15 0 MOTOROLA 4 144 I Format 14 13 1 0 12 11 I 0 I 1 I 10 9 8 7 6 5 4 3 2 0 1 1 I 0 I 0 I 1 1 1 a I 1 I 0 I 1 INSTRUCTION SET CPU32 REFERENCE MANUAL ...

Page 198: ...red if the result is nonzero Unchanged otherwise V Undefined C Set if a borrow decimal is generated Cleared otherwise NOTE Normally the Z condition code bit is set via programming before the start of an operation This allows successful tests for zero results upon completion of multiple precision operations Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 o o o REGISTER Ry o o o o I RIM I R...

Page 199: ...ry Clear CS Carry Set EQ Equal F Never equal GE Greater or Equal GT Greater Than HI High LE Less or Equal Condition Codes Not affected Instruction 15 0 MOTOROLA 4 146 Format 14 13 12 1 0 1 Code 0100 0101 0111 0001 1100 1110 0010 1111 11 Description cc Name Code Description C LS Low or Same 0011 C Z C LT Less Than 1101 NeV NeV Z MI Minus 1011 N 0 NE Not Equal 0110 Z NeV NeV PL Plus 1010 N NeVeZ NeV...

Page 200: ...de Mode Register Addressing Mode Mode Register Dn 000 Reg number Dn xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC dS An Xn 110 Reg number An ds PC Xn bd An Xn 110 Reg number An bd PC Xn NOTE A subsequent NEG S instruction with the same effective address can be used to change the Scc result from TRUE or FALSE to th...

Page 201: ... execution A trace exception occurs if instruction tracing is enabled TO 1 T1 0 when the STOP instruction begins execution If an interrupt request is asserted with a priority higher than the priority level set by the new status register value an interrupt exception occurs otherwise the interrupt request is ignored External reset always initiates reset exception processing Condition Codes Set accor...

Page 202: ...ondition Codes x N z v C X Set to the value of the carry bit N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if an overflow is generated Cleared otherwise C Set if a borrow is generated Cleared otherwise 15 14 13 12 11 10 9 8 7 1 1 0 1 REGISTER OPMODE Instruction Fields Register field Specifies any of the eight data registers Opmode field 6 Lon...

Page 203: ... address register direct is not allowed If the location specified is a destination operand only memory alterable addressing modes are allowed as shown Addressing Mode Mode Register Addressing Mode Mode Register On xxx W 111 000 An xxx L 111 001 An 010 Reg number An data An 011 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC dS An Xn 110 Reg number An dB PC Xn bd An Xn 110 Reg nu...

Page 204: ...n any of the eight address registers Opmode field Specifies the size of the operation 011 Word operation The source operand is sign extended to a long operand and the operation is performed on the address register using all 32 bits 111 Long operation Effective Address field Specifies the source operand All addressing modes are allowed as shown Addressing Mode Mode Dn 000 An 001 An 010 An 011 An 10...

Page 205: ...ust match the operation size Condition Codes x N Z v C X Set to the value of the carry bit N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if an overflow occurs Cleared otherwise C Set if a borrow occurs Cleared otherwise Instruction Format 15 14 13 12 11 10 9 8 0 0 0 0 0 1 0 0 WORD DATA 16 BITS 7 6 SIZE LONG DATA 32 BITS MOTOROLA 4 152 INSTRUC...

Page 206: ...000 Reg number Dn xxx W An xxx L An 010 Reg number An data An 011 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC de An Xn 110 Reg number An de PC Xn bd An Xn 110 Reg number An bd PC Xn Immediate field Data immediately following the instruction If size 00 the data is the low order byte of the immediate word If size 01 the data is the entire immediate word If size 10 the data is ...

Page 207: ... subtracting from address registers the entire destination address register is used regardless of the operation size Condition Codes x N Z v C X Set to the value of the carry bit N Set if the result is negative Cleared otherwise Z Set if the result is zero Cleared otherwise V Set if an overflow occurs Cleared otherwise C Set if a borrow occurs Cleared otherwise Instruction Format 15 14 13 12 11 10...

Page 208: ...ess field Specifies the destination location Only alterable addressing modes are allowed as shown Addressing Mode Mode On 000 An An 010 An 011 An 100 d16 An 101 da An Xn 110 bd An Xn 110 Word and long only CPU32 REFERENCE MANUAL Register Addressing Mode Reg number On xxx W xxx L Reg number An data Reg number An Reg number An Reg number An d16 PC Reg number An da PC Xn Reg number An bd PC Xn INSTRU...

Page 209: ...memory Address registers specified by the instruction access operands from memory using predecrement addressing mode Condition Codes X N z v c X Set to the value of the carry bit N Set if the result is negative Cleared otherwise Z Cleared if the result is nonzero Unchanged otherwise V Set if an overflow occurs Cleared otherwise C Set if a carry occurs Cleared otherwise NOTE Normally the Z conditio...

Page 210: ...er the predecrement addressing mode Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation RIM field Specifies the operand addressing mode o The operation is data register to data register 1 The operation is memory to memory Register Dx Ax field Specifies the source register If RIM 0 specifies a data register If RIM 1 specifies an address register for ...

Page 211: ...fected N Set if the most significant bit of the 32 bit result is set Cleared otherwise Z Set if the 32 bit result is zero Cleared otherwise V Always cleared C Always cleared Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 0 I 1 0 I 0 I 1 I 0 I 0 I 0 I 0 I 1 I 0 I 0 I 0 Instruction Fields Register field Specifies the data register to swap SWAP 2 0 I REGISTER MOTOROLA 4 158 INSTRUCTION SET CPU32 ...

Page 212: ... a signed byte word or long word table containing a linear representation of the dependent variable Y as a function of X In general the independent variable located in the low order word of Ox consists of an 8 bit integer part and an 8 bit fractional part An assumed radix pOint is located between bits 7 and 8 The integer part Ox 15 8 is scaled by the operand size and is used as an offset into the ...

Page 213: ...the register corresponding to the selected size is affected BYTE WORD LONG 31 UNAFFECTED UNAFFECTED RESULT 24 23 UNAFFECTED UNAFFECTED RESULT 16 15 8 7 o UNAFFECTED RESULT RESULT RESULT RESULT RESULT If R 1 TBLSN the result is returned in register Ox without rounding If the size is byte the integer portion of the result is returned in Ox 15 8 The integer portion of a word result is stored in Ox 23...

Page 214: ...e calculated as a fractional number in the range o X 255 On the contrary X should be considered an integer in the range o X 65535 realizing that the table is actually a compressed linear representation of a function in which only every 256th value is actually stored in memory See 4 6 Table Lookup And Interpolation Instructions for more information on theTBLS TBLSN instruction Condition Codes x N Z...

Page 215: ...ister field Addressing Mode Mode Register xxx W 111 000 xxx L 111 001 data d16 PC 111 010 dS PC Xn 111 011 bd PC Xn 111 011 Specifies the destination data register Ox On entry the register contains the interpolation fraction and entry number Oym Dyn field If the effective address mode field is nonzero this operand register is unused and should be zero If the effective address mode field is zero th...

Page 216: ...f a signed byte word or long word table containing a linear representation of the dependent variable Y as a function of X In general the independent variable located in the low order word of Ox consists of an 8 bit integer part and an 8 bit fractional part An assumed radix point is located between bits 7 and 8 The integer part Ox 15 8 is scaled by the operand size and is used as an offset into the...

Page 217: ...x Only the portion of the register corresponding to the selected size is affected BYTE WORD LONG 31 UNAFFECTED UNAFFECTED RESULT 24 23 16 15 UNAFFECTED UNAFFECTED RESULT 8 7 o UNAFFECTED RESULT RESULT RESULT RESULT RESULT If R 1 TABLUN the result is returned in register Ox without rounding If the size is byte the integer portion of the result is returned in Ox 15 8 The integer portion of a word re...

Page 218: ...e calculated as a fractional number in the range o X 255 On the contrary X should be considered to be an integer in the range o X 65535 realizing that the table is actually a compressed linear representation of a function in which only every 256th value is actually stored in memory See 4 6 Table Lookup And Interpolation Instructions for more information on theTBLU TBLUN instruction Condition Codes...

Page 219: ... Register field Addressing Mode Mode Register xxx W 111 000 xxx L 111 001 data d16 PC 111 010 de PC Xn 111 011 bd PC Xn 111 011 Specifies the destination data register Dx On entry the register contains the interpolation fraction and entry number Dym Dyn field If the effective address mode field is nonzero this operand register is unused and should be zero If the effective address mode field is zer...

Page 220: ... of the operand The operation uses a read modify write memory cycle that completes the operation without interruption This instruction supports use of a flag to coordinate several processors Condition Codes x N z v C o 0 X Not affected N Set if the most significant bit of the operand is currently set Z Set if the operand was zero Cleared otherwise V Always cleared C Always cleared Instruction Form...

Page 221: ...s are allowed as shown Addressing Mode MOTOROLA 4 168 Dn An An An An d16 An de An Xn bd An Xn Mode 000 010 011 100 101 110 110 Register Addressing Mode Mode Register Reg number Dn xxx w 111 000 xxx L 111 001 Reg number An data Reg number An Reg number An Reg number An d16 PC Reg number An de PC Xn Reg number An bd PC Xn INSTRUCTION SET CPU32 REFERENCE MANUAL ...

Page 222: ...ber is generated by adding the immediate vector operand to 32 The range of vector operand values is 0 5 thus there are 16 possible vector numbers Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 0 I 1 I 0 I 0 I 1 1 1 I 0 I 0 I Instruction Fields Vector field Specifies the trap vector to be taken CPU32 REFERENCE MANUAL INSTRUCTION SET 6 5 4 1 I 0 I 0 3 I 2 1 0 VECTOR MOTOROLA...

Page 223: ...C Carry Clear 0100 C lS low or Same 0011 CS Carry Set 0101 C IT less Than 1101 EQ Equal 0111 Z MI Minus 1011 F Never equal 0001 0 NE Not Equal 0110 GE Greater or Equal 1100 N V N V Pl Plus 1010 GT Greater Than 1110 N V Z N V Z T Always true 0000 HI High 0010 e z VC Overflow Clear 1000 lE less or Equal 1111 Z N V N V VS Overflow Set 1001 Condition Codes Not affected Instruction Format 15 14 13 12 1...

Page 224: ... is set there is a TRAPV exception vector number 7 If the bit is not set the processor performs no operation and execution continues with the next instruction Condition Codes Not affected Instruction Format 15 14 13 12 11 0 I 1 0 0 I 1 I CPU32 REFERENCE MANUAL 10 9 8 7 1 1 0 I 0 I INSTRUCTION SET 6 5 4 1 1 3 2 o MOTOROLA 4 171 III ...

Page 225: ...es x N Z v C o 0 X Not affected N Set if the operand is negative Cleared otherwise Z Set if the operand is zero Cleared otherwise V Always cleared C Always cleared Instruction Format 15 14 13 12 11 10 9 8 0 1 0 0 1 0 1 0 Instruction Fields Size field Specifies the size of the operation 00 Byte operation 01 Word operation 10 Long operation 7 SIZE MOTOROLA 4 172 INSTRUCTION SET 6 5 4 3 2 o EFFECTIVE...

Page 226: ...000 Reg number On xxx W An 001 Reg number An xxx L An 010 Reg number An data An 011 Reg number An An 100 Reg number An d16 An 101 Reg number An d16 PC dB An Xn 110 Reg number An dB PC Xn bd An Xn 110 Reg number An bd PC Xn Word or long word operation only CPU32 REFERENCE MANUAL INSTRUCTION SET Mode 111 111 111 111 111 111 Register 000 001 100 010 011 011 MOTOROLA 4 173 III ...

Page 227: ... address register then loads the address register with a long word pulled from the top of the stack Condition Codes Not affected Instruction Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 o 0 I 0 I 1 1 I REGISTER Instruction Fields Register field Specifies the address register for the instruction MOTOROLA 4 174 INSTRUCTION SET CPU32 REFERENCE MANUAL ...

Page 228: ...rizing the instructions Table 4 11 is an operation code opcode map that lists an instruction category for each combination of these bits Table 4 11 Operation Code Map Bits 15 12 Operation 0000 Bit Manipulation MOVEPllmmediate 0001 Move Byte 0010 Move Long 0011 Move Word 0100 Miscellaneous 0101 ADDO SUBO Scc DBccITRAPcc 0110 Bcc BSR BRA 0111 MOVEO 1000 ORiDIV SBCD 1001 SUB SUBX 1010 Unassigned Rese...

Page 229: ... Long CHK2 15 14 13 12 11 10 9 8 7 0 0 0 0 0 SIZE 0 1 D A REGISTER 1 010 0 0 Size Field 00 Byte 01 Word 10 Long 8TST Dynamic 15 14 13 12 11 10 9 8 7 0 0 0 0 REGISTER 1 a MOTOROLA 4 176 INSTRUCTION SET 6 6 1 6 1 a 6 1 0 6 0 5 4 3 2 o EFFECTIVE ADDRESS MODE I REGISTER BYTE DATA 8 BITS 5 4 3 2 0 1 1 1 1 BYTE DATA 8 BITS 5 4 3 2 0 1 1 I 1 1 I 0 I 0 I 5 4 3 2 0 EFFECTIVE ADDRESS MODE REGISTER o I 0 I a...

Page 230: ...to Register 110 Transfer Word From Register to Memory 111 Transfer Word From Register to Memory ANDI 15 14 13 12 11 10 9 8 7 6 0 0 0 0 0 0 1 0 SIZE WORD DATA 16 BITS LONG DATA 32 BITS Size Field 00 Byte 01 Word 10 Long ANDI to CCR 14 13 12 11 10 8 7 6 CPU32 REFERENCE MANUAL INSTRUCTION SET 5 4 3 2 o EFFECTIVE ADDRESS MODE I REGISTER 5 4 3 2 o EFFECTIVE ADDRESS MODE I REGISTER 5 4 3 2 o EFFECTIVE A...

Page 231: ... 15 14 13 12 11 10 9 8 7 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Bit Number Field Modulo 32 bit selection BCHG Static 15 14 13 12 11 10 9 8 7 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Bit Number Field Modulo 32 bit selection MOTOROLA 4 178 INSTRUCTION SET 6 0 6 1 5 4 3 2 0 I 1 1 1 I 1 0 I 0 5 4 3 2 0 EFFECTIVE ADDRESS MODE I REGISTER BYTE DATA 8 BITS 5 4 3 2 o EFFECTIVE ADDRESS MODE I REGISTER BYTE DATA 8 BITS ...

Page 232: ...D DATA 16 BITS LONG DATA 32 BITS Size Field 00 Byte 01 Word 10 Long EORI to CCR 15 14 13 12 11 10 9 8 7 6 EORI to SR 15 14 13 12 11 10 9 8 7 6 0 I 0 I 0 I 0 I 1 0 I 1 0 0 1 WORD DATA 16 BITS CPU32 REFERENCE MANUAL INSTRUCTION SET 5 4 3 2 o EFFECTIVE ADDRESS I MODE I REGISTER BIT NUMBER 5 4 3 2 o EFFECTIVE ADDRESS I MODE I REGISTER BIT NUMBER 5 4 3 2 o EFFECTIVE ADDRESS MODE I REGISTER BYTE DATA 8 ...

Page 233: ...Long Note register and mode locations MOVEA 15 14 13 12 11 10 9 DESTINATION 0 0 SIZE REGISTER Size Field 00 Byte 01 Word 10 Long NEGX 15 14 13 12 11 10 9 0 1 0 0 0 0 0 Size Field 00 Byte 01 Word 10 Long I MODE 8 7 0 0 8 7 0 SIZE MOTOROLA 4 180 INSTRUCTION SET 6 1 6 5 4 3 2 o EFFECTIVE ADDRESS MODE I REGISTER BYTE DATA 8 BITS 5 4 3 2 o EFFECTIVE ADDRESS MODE REGISTER o I 0 I 0 o I 0 I 0 5 4 3 2 o E...

Page 234: ...E from CCR 15 14 13 12 11 10 9 8 7 0 1 0 0 0 0 1 0 1 NEG 15 14 13 12 11 10 9 8 7 0 1 0 0 1 0 0 0 SIZE Size Field 00 Byte 01 Word 10 Long CPU32 REFERENCE MANUAL INSTRUCTION SET 6 5 1 6 5 0 6 5 1 6 5 6 5 1 6 5 4 3 2 o EFFECTIVE ADDRESS MODE I REGISTER 4 3 2 o EFFECTIVE ADDRESS MODE I REGISTER 4 3 2 o EFFECTIVE ADDRESS MODE I REGISTER 4 3 2 o EFFECTIVE ADDRESS MODE I REGISTER 4 3 2 o EFFECTIVE ADDRES...

Page 235: ... 0 1 1 I MODE REGISTER NBCD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o EFFECTIVE ADDRESS 0 1 0 0 1 0 0 0 0 0 I MODE REGISTER LINK Long 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o 0111 0 J 0 1 1 J 010JOJ 0 1 0 J o i o 1 1 1 REGISTER SWAP 15 0 BKPT 15 0 MOTOROLA 4 182 14 1 I 14 I 1 I 13 12 11 0 I 0 I 1 13 12 11 0 I 0 I 1 I HIGH ORDER DISPLACEMENT LOW ORDER DISPLACEMENT 10 9 8 7 6 5 4 3 2 1 0 0 I 0 I 0 0 I 1 I 0 I ...

Page 236: ...eld 00 Byte 01 Word 10 Long Register to EA Mask 15 14 13 12 11 10 9 8 7 6 A7 I A6 A5 A4 A3 A2 I A1 I AO I D7 I D6 I EA to Register Mask 15 14 13 12 11 10 9 8 7 6 DO D1 D2 D3 D4 I D5 D6 D7 I AO A1 TST 15 14 13 12 11 10 9 8 7 6 0 1 0 0 1 0 1 0 SIZE Size Field 00 Byte 01 Word 10 Long TAS 15 14 13 12 11 10 9 8 7 6 0 1 0 0 1 0 1 0 1 1 CPU32 REFERENCE MANUAL INSTRUCTION SET 5 5 D5 5 A2 I 5 5 4 3 2 o EFF...

Page 237: ... SIZE a a a a Size Field 0 Long Word Product 1 Quad Word Product TRAP 15 14 13 12 11 10 9 8 7 6 I a I 1 a I 0 I 1 1 1 I 0 I a I 1 LINK Word 13 12 9 8 7 6 UNLK 15 14 13 12 11 10 9 8 7 6 0 I 1 I a I 0 I 1 I 1 1 I 0 I a I 1 MOTOROLA 4 184 INSTRUCTION SET 5 4 3 2 0 I 1 I 1 I 1 I 0 I 1 I 0 I 5 4 3 2 0 I 1 1 I 1 I 1 I 0 I 0 I 5 4 3 2 0 EFFECTIVE ADDRESS MODE REGISTER o I o I 0 REGISTERDh 5 4 3 2 o EFFEC...

Page 238: ... STOP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 1 1 1 0 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0 1 1 1 0 I IMMEDIATE DATA RTE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 1 1 1 0 1 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 Format Offset Word in stack frame 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 FORMAT 1 0 1 0 1 VECTOR OFFSET Format Field Four bits imply frame size only values 000 0010 and 1000 1011 are used RTD 15...

Page 239: ... 001 DFC 802 CAAR 002 CACR 803 MSP 800 USP 804 ISP JSR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 EFFECTIVE ADDRESS 0 1 0 0 1 1 1 0 1 0 I MODE REGISTER JMP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 EFFECTIVE ADDRESS 0 1 0 0 1 1 1 0 1 1 I MODE REGISTER ADDQ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 EFFECTIVE ADDRESS 0 1 0 1 DATA 0 SIZE I MODE REGISTER Data Field Three bits of immediate data 000 111 represent values of 1 7 ...

Page 240: ...2 EFFECTIVE ADDRESS 0 1 0 1 DATA 1 SIZE I MODE REGISTER Data Field Three bits of immediate data 000 111 represent values of 1 7 000 represents 8 Size Field 00 Byte 01 Word 10 Long 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o I 1 I 1 I o I CONDITION I 8 BIT DISPLACEMENT 16 BIT DISPLACEMENT IF 8 BIT DISPLACEMENT 00 32 BIT DISPLACEMENT IF 8 BIT DISPLACEMENT FF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o I 1 I 1 I o I...

Page 241: ...0 100 Word 001 101 15 14 13 12 11 10 1 0 0 0 REGISTER 15 14 13 12 11 10 1 0 0 0 REGISTER 9 9 8 7 OPMODE Long 010 110 8 0 8 1 7 1 7 1 6 5 4 3 2 EFFECTIVE ADDRESS MODE Operation ea Dn Dn Dn ea ea 6 5 4 3 I REGISTER 2 EFFECTIVE ADDRESS 1 I MODE REGISTER 6 5 4 3 2 EFFECTIVE ADDRESS 1 I MODE REGISTER o o o o o 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 o 1 REGISTER Ry ololololRiMI REGISTERRx RIM Field 0 Data ...

Page 242: ...X CMP 15 14 13 12 11 10 9 8 7 6 I 1 I o I REGISTER Ax SIZE Size Field 00 Byte 01 Word 10 Long RIM Field 0 Data Register to Data Register 1 Memory to Memory If RIM 0 both registers must be data registers 5 4 3 2 1 0 o o I RIM I REGISTERRy If RIM 1 both registers must be address registers for Predecrement Addressing mode 15 14 13 12 11 10 9 1 0 1 Opmode Field 1 Byte 000 REGISTER Word 001 8 7 OPMODE ...

Page 243: ... 10 9 REGISTER Word 001 101 MULU Word 15 14 13 12 11 10 9 1 1 0 0 REGISTER 8 7 6 5 OPMODE Operation An ea CCR 8 7 6 5 OPMODE 4 3 2 EFFECTIVE ADDRESS MODE I REGISTER 4 3 2 EFFECTIVE ADDRESS MODE I REGISTER Long Operation 110 ea Dn ea 8 7 6 5 4 3 2 o o 0 1 I SIZE 0 I 0 I 1 I REGISTERAy 8 7 OPMODE Long 010 110 8 7 0 1 6 5 4 3 2 EFFECTIVE ADDRESS MODE Operation ea Dn Dn Dn ea ea 6 5 4 3 I REGISTER 2 E...

Page 244: ...EGISTER Rx Opmode Field Specifies type of exchange 01000 Data Register Exchange 01001 Address Register Exchange 8 7 6 5 4 3 2 0 OPMODE REGISTERRy 10001 Data Register I Address Register Rx specifies data register Ry specifies address register 15 14 13 12 11 1 1 Opmode Field 0 1 Byte 000 100 10 REGISTER Word 001 101 9 8 7 OPMODE Long 010 110 6 5 4 3 2 EFFECTIVE ADDRESS MODE Operation ea Dn Dn Dn ea ...

Page 245: ...Register Shift Count LSL LSR Register 15 14 13 12 11 10 9 8 7 6 I 1 I 1 I 1 I 0 ICOUNTIREGISTERI dr SIZE Count Register Field If I R Field 0 Specifies Shift Count If I R Field 1 Specifies Data Register that contains Shift Count dr Field 0 Right 1 Left Size Field 00 Byte 01 Word 10 Long I R Field 0 Immediate Shift Count 1 Register Shift Count ROXL ROXR Register 15 14 13 12 11 10 9 8 7 6 I 1 I 1 I 1...

Page 246: ...1 1 0 0 0 0 dr 1 1 dr Field 0 Right 1 Left LSL LSR Memory 15 14 13 12 11 10 9 8 7 6 1 1 1 0 0 0 1 dr 1 1 dr Field 0 Right 1 Left ROXL ROXR Memory 15 14 13 12 11 10 9 8 7 6 1 1 1 0 0 1 0 dr 1 1 dr Field 0 Right 1 Left ROL ROR Memory 15 14 13 12 11 10 9 8 7 6 1 1 1 0 0 1 1 dr 1 1 dr Field 0 Right 1 Left CPU32 REFERENCE MANUAL INSTRUCTION SET 5 i r 5 5 5 5 4 3 2 0 REGISTER 4 3 2 0 EFFECTIVE ADDRESS M...

Page 247: ...ata Register Interpolate 14 13 12 11 10 9 8 7 6 R Field 0 Unrounded 1 Rounded TBLS TBLSN Lookup and Interpolate 15 14 13 12 11 10 9 8 7 6 1 1 1 1 1 0 0 0 0 0 0 REGISTER Dx 1 R 0 1 SIZE R Field 0 Unrounded 1 Rounded MOTOROLA 4 194 INSTRUCTION SET 5 4 3 2 0 0 0 5 4 3 2 0 REGISTER Dym REGISTER Dyn 5 4 3 2 0 EFFECTIVE ADDRESS MODE REGISTER o I 0 I 0 o I 0 1 0 5 4 3 2 0 REGISTER Dym REGISTER Dyn 5 4 3 ...

Page 248: ...y calculated linear interpolations The following examples show how to compress tables and use fewer interpolation levels between table entries Example 1 see Figure 4 3 demonstrates table lookup and interpolation for a 257 entry table allowing up to 256 interpolation levels between entries Example 2 see Figure 4 4 reduces table length for the same data to four entries Example 3 see Figure 4 5 demon...

Page 249: ...n in Figure 4 3 the function is linear within the range 32768 X 49152 Table entries within this range are as follows MOTOROLA 4 196 Entry X Y Number Value Value 128 32768 1311 162 41472 1659 163 41728 1669 164 41984 1679 165 42240 1690 192 49152 1966 These values are the end points of the range All entries between these points fallon the line INSTRUCTION SET CPU32 REFERENCE MANUAL ...

Page 250: ...8 15 A3 163 Interpolation Fraction Dx 0 7 80 128 Using this information the table instruction calculates dependent variable Y Y 1669 128 1679 1669 256 1674 4 6 2 Table Example 2 Compressed Table I z w o z w a w o y CPU32 REFERENCE MANUAL 256 512 786 INDEPENDENT VARIABLE Figure 4 4 Table Example 2 INSTRUCTION SET 1024 MOTOROLA 4 197 ...

Page 251: ...ue 2 512 1311 3 786 1966 Since the table is reduced from 257 to 5 entries independent variable X must be scaled appropriately In this case the scaling factor is 64 and the scaling is done by a single instruction LSR W 6 Ox Thus Ox now contains the following bit pattern 31 16 15 0 NOT USED 00000010100011101 Table Entry Offset Dx 8 15 02 2 Interpolation Fraction Dx 0 7 8E 142 Using this information ...

Page 252: ...se a table instruction within an interpolation subroutine Independent variable X is calculated as an 8 bit value allowing 16 levels of interpolation on a 17 entry table X is passed to the subroutine which returns an 8 bit result The subroutine uses the following data based on the function shown in Figure 4 5 CPU32 REFERENCE MANUAL INSTRUCTION SET MOTOROLA 4 199 III ...

Page 253: ...and the third column is the result returned by the subroutine The following value has been calculated for independent variable X 31 16 15 0 NOT USED 0000000010111101 Since X is an 8 bit value the upper four bits are used as a table offset and the lower four bits are used as an interpolation fraction The following results are obtained from the subroutine Table Entry Offset Dx 4 7 8 11 Interpolation...

Page 254: ...polation Fraction Dx 0 7 DO 208 Thus Y is calculated as follows Y 80 208 64 80 256 67 4 6 4 Table Example 4 Maintaining Precision In this example three table lookup and interpolation TLI operations are performed and the results are summed The calculation is done once with the result of each TLI rounded before addition and once with only the final result rounded Assume that the result of the three ...

Page 255: ... 0000 0110 0001 0101 0000 0110 0001 The second result is preferred The following code sequence illustrates how addition of a series of table interpolations can be performed without loss of precision in the intermediate results LO TBLSN B TBLSN B TBLSN B AOO L AOO L ASR L BCC B AOOQ B L1 MOTOROLA 4 202 ea Ox ea Ox ea OI Ox Om Om DI 8 01 L1 1 01 Long addition avoids problems with carry Move radix po...

Page 256: ... word if TBLSN is word Increased size is necessary because a larger number of significant digits is needed to accommodate the scaled fractional results of the 20 TLI 4 7 Nested Subroutine Calls The LINK instruction pushes an address onto the stack saves the stack address at which the address is stored and reserves an area of the stack for use Using this instruction in a series of subroutine calls ...

Page 257: ...III MOTOROLA 4 204 INSTRUCTION SET CPU32 REFERENCE MANUAL ...

Page 258: ...the transition from normal processing of a program to normal processing of system routines interrupt routines and other exception handlers Exception processing includes the stack operations the exception vector fetch and the filling of the instruction pipeline caused by an exception Exception processing ends when execution of an exception handler routine begins Refer to SECTION 6 EXCEPTION PROCESS...

Page 259: ...structions executed in supervisor level are normally classified as supervisor references and the values of the function codes on FC2 FCO refer to supervisor address spaces All exception processing is performed at the supervisor level All bus cycles generated during exception processing are supervisor references and all stack accesses use the supervisor stack pointer Instructions that have importan...

Page 260: ...her of two ways If the frame was generated by an interrupt breakpoint trap or instruction exception the status register and program counter are restored to the values saved on the supervisor stack and execution resumes at the restored program counter address with access level determined by the S bit of the restored status register If the frame was generated by a bus error or an address error excep...

Page 261: ...space All M68000 processors use CPU space for interrupt acknowledge cycles The CPU32 also uses CPU space for breakpoint acknowledge and the LPSTOP broadcast Supervisor programs can use the MOVES instruction to access all address spaces including user spaces and CPU address space Although the MOVES instruction can be used to generate CPU space cycles doing so may interfere with proper system operat...

Page 262: ...ccess is not supported by the CPU32 processor This space is reserved for future use 5 3 1 3 Type 0010 Coprocessor Access This type of access is not supported by the CPU32 processor This space is reserved for future use 5 3 1 4 Type 0011 Internal Register Access Type 0011 space is used to access certain critical system configuration or control registers The CPU32 external bus interface interrupt ma...

Page 263: ...A A A A A A A AI A 15 12 are used as 1 of 16 external chip selects A 11 8 are used as 1 of 16 internal module selects A 7 0 are used as 1 of 256 module register addresses 5 3 1 5 Type 1111 Interrupt Acknowledge Interrupt acknowledge is a CPU space type used for interrupt acknowledge A 4 1 indicate the encoded interrupt level being acknowledged 31 5 4 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1...

Page 264: ...ctdrs are reserved for user definition as interrupt vectors Except for the reset vector each vector in the table is one long word in length The reset vector is two long words in length Refer to Table 6 1 for information on vector assignment CAUTION Because there is no protection on the 64 processor defined vectors external devices can access vectors reserved for internal purposes this practice is ...

Page 265: ...4 96 060 SD Spurious Interrupt 25 100 064 SD Level 1 Interrupt Autovector 26 104 068 SD Level 2 Interrupt Autovector 27 108 06C SD Level 3 Interrupt Autovector 28 112 070 SD Level 4 Interrupt Autovector 29 116 074 SD Level 5 Interrupt Autovector 30 120 078 SD Level 6 Interrupt Autovector 31 124 07C SD Level 7 Interrupt Autovector 32 47 128 080 SD Trap Instruction Vectors 0 15 188 OBC 48 58 192 OCO...

Page 266: ...s in the status register are changed the S bit is set establishing supervisor access level and bits T1 and TO are cleared disabling tracing For reset and interrupt exceptions the interrupt priority mask is also updated Next the exception number is obtained For interrupts the number is fetched from CPU space F the bus cycle is an interrupt acknowledge For all other exceptions internal logic provide...

Page 267: ...mats are peculiar to a particular M68000 Family processor format 0000 is always legal and always indicates that only the first four words of a frame are present See 6 4 CPU32 Stack Frames for a complete discussion of exception stack frames SP AFTER STACKING CI w w a c a w r o E j o 15 STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW FORMAT I VECTOR OFFSET OTHER PROCESSOR STATE INFORMATION ...

Page 268: ... exception or execution of a handler routine Priority assignment governs the order in which exception processing occurs not the order in which exception handlers are executed As a general rule when simultaneous exceptions occur the handler routines for III lower priority exceptions are executed before the handler routines for higher priority exceptions For example consider the arrival of an interr...

Page 269: ...r base register to zero 00000000 5 Generates a vector number to reference the reset exception vector 6 Loads the first long word of the vector into the interrupt stack pointer 7 Loads the second long word of the vector into the program counter 8 Fetches and initiates decode of the first instruction to be executed Figure 6 2 is a flowchart of the reset exception After initial instruction prefetches...

Page 270: ...2 IO VBR OTHERWISE S VECTOR 0 OTHERWISE PC VECTOR 1 OTHERWISE BEGIN INSTRUCTION EXECUTION BUSERRORI ADDRESS ERROR DOUBLE BUS FAULT Figure 6 2 Reset Operation Flowchart CPU32 REFERENCE MANUAL EXCEPTION PROCESSING MOTOROLA 6 7 ...

Page 271: ...rand access is attempted Exception processing for bus error exceptions follows the regular sequence but context preservation is more involved than for other exceptions because a bus exception can be initiated while an instruction is executing Several bus error stack format organizations are utilized to provide additional information regarding the nature of the fault First any register altered by a...

Page 272: ...ess and the current instruction program counter points to the instruction that caused the exception If an address error occurs during exception processing for a bus error another address error or a reset the processor halts 6 2 4 Instruction Traps Traps are exceptions caused by instructions They arise from either processor recognition of abnormal conditions during instruction execution or from use...

Page 273: ...hen a breakpoint instruction is executed the CPU32 performs a read from CPU space 0 at a location corresponding to the breakpoint number See 5 3 Types of Address Space If this bus cycle is terminated by BERR the processor performs illegal instruction exception processing If the bus cycle is terminated by DSACK the processor uses the data returned to replace the breakpoint in the instruction pipeli...

Page 274: ... instruction that contains an undefined register specification field in the first extension word or if it contains an indexed addressing mode extension word with bits 5 4 00 or bits 3 0 0000 If an illegal instruction is fetched during instruction execution an illegal instruction exception occurs This facility allows the operating system to detect program errors or to emulate instructions in softwa...

Page 275: ...instructions can be executed only at the supervisor access level An attempt to execute one of these instructions at the user level will cause an exception The privileged exceptions are as follows AND Immediate to SR EOR Immediate to SR LPSTOP MOVE from SR MOVE to SR MOVE USP MOVEC MOVES OR Immediate to SR RESET RTE STOP Exception processing for privilege violations is nearly identical to that for ...

Page 276: ... traced in this way No exception occurs if a branch is not taken When T 1 0 10 at the beginning of instruction execution a trace exception will be generated when execution is complete If the instruction is not executed either because an interrupt is taken or because the instruction is illegal unimplemented or privileged an exception is not generated At the present time T 1 0 11 is an undefined con...

Page 277: ...uction while tracing is enabled no trace exception will occur because the instruction is not executed This is particularly important to an emulation routine that performs an instruction function adjusts the stacked program counter to beyond the unimplemented instruction and then returns The status register on the stack must be checked to determine if tracing is on before the return is executed If ...

Page 278: ...ssing occurs as follows First the processor makes an internal copy of the status register After the copy is made the processor state bits in the status register are changed the S bit is set establishing supervisor access level and bits T1 and TO are cleared disabling tracing Then priority level is set to the level of the interrupt and the processor fetches a vector number from the interrupting dev...

Page 279: ...n RTE is executed the processor examines the stack frame on top of the supervisor stack to determine if it is valid and determines what type of context restoration must be performed See 6 4 CPU32 Stack Frames for a description of stack frames For a normal four word frame the processor updates the status register and program counter with data pulled from the stack increments the supervisor stack pO...

Page 280: ...possible and restoring the processor state Saving and restoring the processor state are described in the following paragraphs The stack contents are identified by the special status word SSW In addition to identifying the fault type represented by the stack frame the SSW contains the internal processor state corresponding to the fault 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 I lP I MV I 0 I 1R I B1 I B...

Page 281: ... source when a bus error exception was processed Pending breakpoint status is stacked regardless of the type of bus error exception o Breakpoint not pending 1 Breakpoint pending BO indicates that a breakpoint exception was pending on channel 0 internal breakpoint source when the bus error exception was processed Pending breakpoint status is stacked regardless of the type of bus error exception o B...

Page 282: ...e SSW SIZ field shows operand size remaining when a fault was detected This field does not indicate the initial size of the operand It also does not necessarily indicate the proper status of a dynamically sized bus cycle Dynamic sizing occurs on the external bus and is transparent to the CPU Byte size is shown only when the original operand was a byte The field is reloaded into the bus controller ...

Page 283: ...a I a I LG I SIZ FUNC TR B1 and BO are set if the corresponding exception is pending when the BERR exception is taken Status regarding the faulted bus cycle is reflected in the SSW LG SIZ and FUNC fields The remainder of the stack contains the program counter of the next unexecuted instruction the current status register the address of the faulted memory location and the contents of the data buffe...

Page 284: ... III Faults During MOVEM Operand Transfer Bus faults that occur as a result of MOVEM operand transfer are classified as type III faults MOVEM Instruction prefetch faults are type II faults Type III faults cause an immediate exception that aborts the current instruction None of the registers altered during execution of the faulted instruction are restored prior to execution of the fault handler Thi...

Page 285: ... contains the following bit pattern 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 I 1 I 0 I 0 I 1R I B1 I BO I 0 I 0 I 0 I 1 I LG I SIZ FUNC TR B1 and BO are set if a corresponding exception is pending when the BERR exception is taken The contents of the faulted exception stack frame are included in the bus fault stack frame The pre exception status register and the format vector word of the faulted frame a...

Page 286: ...eleased Writes via RTE An exception handler can use the RTE instruction to complete a faulted bus cycle When RTE executes the fault address data output buffer program counter and status register are restored from the stack Any pending breakpoint or trace exceptions as indicated by TR B1 and 80 in the stacked SSW are requeued during SSW restoration The RR bit in the SSW is checked during the unstac...

Page 287: ...ddress is saved in the stack frame However the opcode effective address field must be examined to determine how to update the address register and program counter when the instruction is complete Adjust the mask to account for operands already transferred Subtract the stacked operand transfer count from 16 to obtain the number of operands transferred Scan the mask using this count value Each time ...

Page 288: ...referred method of MOVEM bus fault recovery is to correct the cause of the fault and then execute an RTE instruction without altering the stack contents The RTE recognizes that MOVEM was in progress when a fault occurred restores the appropriate machine state refetches the instruction repeats the faulted transfer and continues the instruction MOVEM is the only instruction continued upon return fro...

Page 289: ...acking the BERR exception stacking was successfully completed This is an extremely improbable occurrence but the CPU32 supports recovery from it Once the exception handler determines that the fault has been corrected recovery can proceed as described previously If the fault cannot be corrected move the supervisor stack to another area of memory copy all valid stack frames to the new stack create a...

Page 290: ...TOR OFFSET FAULTED INSTRUCTION PROGRAM COUNTER HIGH FAULTED INSTRUCTION PROGRAM COUNTER LOW Figure 6 4 Format 2 Six Word Stack Frame Hardware breakpoints also utilize this format The faulted instruction program counter value is the address of the instruction executing when the breakpoint was sensed Usually this is the address of the instruction that caused the breakpoint but because released write...

Page 291: ...nal Transfer Count Register The microcode revision number is checked before a BERR stack frame is restored via RTE In a multiprocessor system this check insures that a processor using stacked information is at the same revision level as the processor that created it The transfer count is ignored unless the MV bit in the stacked SSW is set If the MV bit is set the least significant byte of the inte...

Page 292: ...ess of a dynamically sized bus cycle is the address of the upper byte regardless of the byte that caused the error SP 02 06 08 OC 10 14 16 15 o STATUS REGISTER RETURN PROGRAM COUNTER HIGH RETURN PROGRAM COUNTER LOW 1 I 1 I 0 I 0 I VECTOR OFFSET FAULTED ADDRESS HIGH FAULTED ADDRESS LOW DBUFHIGH DBUFLOW CURRENT INSTRUCTION PROGRAM COUNTER HIGH CURRENT INSTRUCTION PROGRAM COUNTER LOW INTERNAL TRANSFE...

Page 293: ...ATUS WORD Figure 6 7 Format C BERR Stack on MOVEM Operand 15 o STATUS REGISTER NEXT INSTRUCTION PROGRAM COUNTER HIGH NEXT INSTRUCTION PROGRAM COUNTER LOW 1 I 1 J 0 I 01 VECTOR OFFSET FAULTED ADDRESS HIGH FAULTED ADDRESS LOW PRE EXCEPTION STATUS REGISTER FAULTED EXCEPTION FORMATNECTOR WORD FAULTED INSTRUCTION PROGRAM COUNTER HIGH SIX WORD FRAME ONLy FAULTED INSTRUCTION PROGRAM COUNTER LOW SIX WORD ...

Page 294: ...Emulation When an attempt is made to execute an illegal instruction an illegal instruction exception occurs Unimplemented instructions F line A line utilize separate exception vectors to permit efficient emulation of unimplemented instructions in software See 6 2 8 Illegal or Unimplemented Instructions for more information 7 1 CPU32 Integrated Development Support In addition to standard MC68000 fa...

Page 295: ...d DC parametric mismatches and restrictions on cable length are minimized IN CIRCUIT EMULATOR TARGET l SYSTEM A I TARGET 1 I 1 1 PROCESSOR I Figure 7 1 In Circuit Emulator Configuration TARGET SYSTEM I TARGET I BUS STATE l PROCESSOR I ANALYZER Figure 7 2 Bus State Analyzer Configuration Deterministic Opcode Tracking Overview CPU32 function code outputs are augmented by two supplementary signals th...

Page 296: ...ledged Acknowledged breakpoints can initiate either exception processing or background debug mode BOM See 6 2 6 Hardware Breakpoints for more information 7 2 Background Debug Mode BOM BOM is an alternate CPU32 operating mode Ouring BOM normal instruction execution is suspended and special microcode performs debugging functions under external control Figure 7 3 is a BOM block diagram MICROCODE EXEC...

Page 297: ... negation of RESET 80M enable logic must be designed with special care If hold time on BKPT after the trailing edge of RESET extends into the first bus cycle following reset the bus cycle could inadvertently be tagged with a breakpoint Refer to the system integration module user s manual for timing information 7 2 2 80M Sources When 80M is enabled any of several sources can cause the transition fr...

Page 298: ...e temporarily bypassed so that its origin can be isolated and eliminated 7 2 2 4 Peripheral Breakpoints CPU32 peripheral breakpoints are implemented in the same wa xternal breakpoints peripherals request breakpoints by asserting the BKPT Signal Consult the appropriate peripheral user s manual for additional details on the generation of peripheral breakpoints 7 2 3 Entering BDM When the processor d...

Page 299: ...to be shifted out as the next command is read This process is repeated for each command until the CPU returns to normal operating mode 7 2 5 Background Mode Registers 8DM processing uses three special purpose registers to keep track of program context during development A description of each follows 7 2 5 1 Fault Address Register FAR The FAR contains the address of the faulting bus cycle immediate...

Page 300: ...K SHIFT OUT 17 BITS DISABLE SHIFT CLOCK EXECUTE COMMAND LOAD NOT READY RESPONSE PERFORM COMMAND STORE RESULTS READ RESULTSINEW COMMAND LOAD COMMAND REGISTER ENABLE SHIFT CLOCK SHIFT IN OUT 17 BITS DISABLE SHIFT CLOCK READ RESULT REGISTER YES CONTINUE Figure 7 4 80M Command Execution Flowchart CPU32 REFERENCE MANUAL DEVELOPMENT SUPPORT MOTOROLA 7 7 ...

Page 301: ...pon negation of FREEZE the serial subsystem is disabled and the signals revert to IPIPE IFETCH functionality 7 2 7 Serial Interface Communication with the CPU32 during BOM occurs via a dedicated serial interface which shares pins with other development features The BKPT signal becomes the serial clock DSCLK serial input data DSI is received on IFETCH and serial output data OSO is transmitted on IP...

Page 302: ...Encoding Data Message Type xxxx Valid Data Transfer FFFF Command Complete Status OK 0000 Not Ready with Response Come Again 0001 BERR Terminated Bus Cycle Data Invalid FFFF Illegal Command Command and data transfers initiated by the development system should clear bit 16 The current implementation ignores this bit however Motorola reserves the right to use this bit for future enhancements CPU32 RE...

Page 303: ...nter CPU DEVELOPMENT SYSTEM INSTRUCTION REGISTER BUS DATA 6 0 16 I RCVDATALATCH I I COMMAND LATCH I SERIAL IN DSI PARALLEL IN PARALLEL OUT SERIAL OUT DSO l W PARALLEL IN SERIAL IN SERIAL OUT PARALLEL OUT U 16 STATUS RESULT LATCH EXECUTION STlus f6 UNIT SYNCHRONIZE DATA MICROSEQUENCER tt I I CONTROL I DSCLK I CONTROL SERIAL LOGIC j I LOGIC CLOCK Figure 7 5 Debug Serial 1 0 Block Diagram MOTOROLA 7 ...

Page 304: ...SCLK I DSI SAMPLE WINDOW INTERNAL SYNCHRONIZED DSCLK INTERNAL SYNCHRONIZED DSI DSO CLKOUT Figure 7 6 Serial Interface Timing Diagram The serial state machine begins a sequence of events based on the rising edge of the synchronized OSCLK see Figure 7 6 Synchronized serial data is transferred to the input shift register and the received bit counter is decremented One half clock period later the outp...

Page 305: ... user can use the state change on DSO to signal hardware that the next serial transfer may begin A timeout of sufficient length to trap error conditions that do not change the state of DSO should also be incorporated into the design Hardware interlocks in the CPU prevent result data from corrupting serial transfers in progress 7 2 7 2 Development System Serial Logic The development system as the m...

Page 306: ...ned previously all timing within the CPU is derived from the rising edge of the clock the falling edge is effectively ignored FORCE_BGND J LLI 1 11 11 1Iu 1 1 ___________________ FREEZE _ _ _ _ L Figure 7 8 BKPT Timing for Forcing BOM Figure 7 9 represents a sample circuit providing for both BKPT assertion methods As the name implies FORCE_BGND is used to force a transition into BDM by the asserti...

Page 307: ...ock frequency is implementation dependent and may range from OC to the maximum specified frequency Although performance considerations might dictate a hardware implementation software solutions are not precluded provided serial bus timing is maintained 7 2 8 Command Set Following is a description of the command set available in BOM 7 2 8 1 Command Format The following standard bit format is utiliz...

Page 308: ...this field may be interpreted differently Register Field In most commands this field specifies the register number when operating on an address or data register Extension Words as required At this time no command requires an extension word to specify fully the operation to be performed but some commands require extension words for w addresses or immediate data Addresses require two extension words...

Page 309: ...mented in which case the response data is the illegal command encoding If an illegal command response occurs the development system should retransmit the command NOTE The not ready response can be ignored unless a memory bus cycle is in progress Otherwise the CPU can accept a new serial transfer with eight system clock periods In the third cycle the development system supplies the low order 16 bit...

Page 310: ...RESULTS FROM PREVIOUS COMMAND RESPONSES FROM THE CPU NONSERIAL RELATED ACTIVITY SEQUENCE TAKEN IF BUS ERROR OR ADDRESS ERROR OCCURS ON MEMORY ACCESS HIGH AND LOW ORDER 16 BITS OF RESULT Figure 7 10 Command Sequence Diagram Example 7 2 8 3 Command Set Summary The 8DM command set is summarized in Table 7 4 Subsequent paragraphs contain detailed descriptions of each command CPU32 REFERENCE MANUAL DEV...

Page 311: ... to the memory location WRITE specified by the long word address The destination function code register DFC register determines the address space accessed Used in conjunction with the READ command to dump large blocks of memory An initial READ is executed DUMP to set up the starting address of the block and to retrieve the first result Subsequent operands are retrieved with the DUMP command Used i...

Page 312: ...nd Data None Result Data The contents of the selected register are returned as a long word value The data is returned most significant word first 7 2 8 5 Write AID Register WAREG WDREG The operand long word data is written to the specified address or data register All 32 bits of the register are altered by the write Command Format 15 14 13 12 11 10 9 8 7 6 o I 0 I 1 o I 0 I 0 o I 0 I 1 I 0 I CPU32...

Page 313: ...egister write is complete 7 2 8 6 Read System Register RSREG The specified system control register is read All registers that can be read in supervisor mode can be read in 8DM Several internal temporary registers are also accessible Command Format 15 14 13 12 11 10 9 8 7 6 5 4 3 o o 1 0 1 1 o 1 0 1 1 010111010101 REGISTER Command Sequence Operand Data None MOTOROLA 7 20 DEVELOPMENT SUPPORT CPU32 R...

Page 314: ...upervisor Stack Pointer SSP 1101 Source Function Code Register SFC 1110 Destination Function Code Register DFC 1111 Temporary Register A ATEMP 1000 Fault Address Register FAR 1001 Vector Base Register VBR 1010 7 2 8 7 Write System Register WSREG Operand data is written into the specified system control register All registers that can be written in supervisor mode can be written in BDM Several inte...

Page 315: ...ruction Program Counter PCC 0001 Status Register SR 1011 User Stack Pointer USP 1100 Supervisor Stack Pointer SSP 1101 Source Function Code Register SFC 1110 Destination Function Code Register DFC 1111 Temporary Register A ATEMP 1000 Fault Address Register FAR 1001 Vector Base Register VBR 1010 7 2 8 8 Read Memory Location READ Read the sized data at the memory location specified by the long word ...

Page 316: ...successful read operation returns data bit 16 cleared If a bus or address error is encountered the returned data is 10001 7 2 8 9 Write Memory Location WRITE Write the operand data to the memory location specified by the long word address The destination function code DFC register determines the address space accessed Only absolute addressing is supported Valid data sizes include byte word and lon...

Page 317: ...s the data Byte data is transmitted as a 16 bit word justified in the least significant byte 16 and 32 bit operands are transmitted as 16 and 32 bits respectively Result Data Successful write operations return a status of OFFFF Bus or address errors on the write cycle are indicated by the assertion of bit 16 in the status message and by a data pattern of 0001 MOTOROLA 7 24 DEVELOPMENT SUPPORT CPU3...

Page 318: ... operand size and store the updated address back in the temporary register NOTE The DUMP command does not check for a valid address in the temporary register DUMP is a valid command only when preceded by another DUMP or by a READ command Otherwise the results are undefined The NOP command can be used for inter command padding without corrupting the address pointer The size field is examined each t...

Page 319: ...erand Subsequent operands are written with the FILL command The initial address is incremented by the operand size 1 2 or 4 and is saved in a temporary register Subsequent FILL commands use this address increment it by the current operand size and store the updated address back in the temporary register NOTE The FILL command does not check for a valid address in the temporary register FILL is a va...

Page 320: ...6 and 32 bits respectively Result Data Status is returned as in the WRITE command OFFFF for a successful III operation and 10001 for a bus or address error during write 7 2 8 12 Resume Execution GO The pipeline is flushed and refilled before normal instruction execution is resumed Prefetching begins at the return PC and current privilege level If either the PC or SR is altered during BDM the updat...

Page 321: ...8 7 6 5 4 3 2 o o I 0 I a I 0 I 0 I 0 I 0 I 0 I 0 I 0 I Command Sequence Operand Data None Result Data None 7 2 8 13 Call User Code CALL This instruction provides a convenient way to patch user code The return PC is stacked at the location pointed to by the current SP The stacked PC serves as a return address to be restored by the RTS command that terminates the patch routine After stacking is com...

Page 322: ...ering BOM For address error the PC does not reflect the true return PC Instead the stacked fault address is the odd return PC Command Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o 0101010101010101010101 Command Sequence Operand Data The 32 bit operand data is the starting location of the patch routine which is the initial PC upon exiting BDM ResuIt Data None As an example consider the following code ...

Page 323: ...AT 2 Enter BOM 3 Execute CALL command to MISSING 4 Exit BOM 5 Execute MISSING code 6 Return to user program 7 2 8 14 Reset Peri pherals RST RST asserts RES ET for 512 clock cycles The CPU is not reset by this command This command is synonymous with the CPU RESET instruction Command Format 15 14 13 12 11 10 9 8 7 6 5 4 3 2 o o I 0 I 0 I 0 I 0 I 1 o I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I Command Sequ...

Page 324: ... 2 0 o I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 Command Sequence Operand Data None Result Data The command complete response OFFFF is returned during the next shift operation E 7 2 8 16 Future Commands Unassigned command opcodes are reserved by Motorola for future expansion All unused formats within any revision level will perform a NOP and return the ILLEGAL command response CP...

Page 325: ...sociated prefetch followed immediately by a second prefetch That is IFETCH remains asserted for three clocks two clocks indicating the flush fetch and a third clock signaling the second fetch These two operations are easily discerned if the tracking logic samples IFETCH on the two rising edges of CLKOUT which follow the address strobe data strobe during show cycles falling edge Three clock and slo...

Page 326: ...he pipeline IRS IRe and IRA IRS IRA is refilled during the next instruction fetch bus cycle Data loaded into IRA propagates automatically through subsequent empty pipeline stages Signals that show the progress of instructions through IRS and IRe are necessary to accurately monitor pipeline operation These signals are provided by IRA and IRS validity bits When a pipeline advance occurs the validity...

Page 327: ...uctions using immediate addressing begin executing and initiate a second pipeline advance at the same time IPIPE will not be negated between the two indications which implies the need for a state machine to track the state of IPIPE The state machine can be resynchronized during periods of inactivity on the signal 7 3 3 Opcode Tracking during Loop Mode IPIPE and IFETCH continue to work normally dur...

Page 328: ...endency 8 1 Resource Scheduling The CPU32 contains several independently scheduled resources The organization of these resources within the CPU32 is shown in Figure 8 1 Some variation in instruction execution timing results from concurrent resource utilization Because resource scheduling is not directly related to instruction boundaries it is impossible to make an accurate prediction of the time r...

Page 329: ...efilled by the prefetch controller as it empties Stage A of the instruction pipeline is a buffer Prefetches completed on the bus before stage B empties are temporarily stored in this buffer Instruction words instruction operation words and all extension words are decoded at stage B Residual decoding and execution take place in stage C Each pipeline stage has an associated status bit that shows whe...

Page 330: ...nd accesses previously requested by the microsequencer Additional state information permits the controller to inhibit prefetch requests when a change in instruction flow e g a jump or branch instruction is anticipated In a typical program 10 to 25 percent of the instructions causes a change of flow Each time a change occurs the instruction pipeline must be flushed and refilled from the new instruc...

Page 331: ...is the time measured in clock cycles that an instruction executes concurrently with the previous instruction As shown in Figure 8 2 portions of instructions A and B execute simultaneously so that total execution time is reduced Because portions of instructions Band C also overlap overall execution time for all three instructions is also reduced Each instruction contributes to the total overlap tim...

Page 332: ...on is given and are based on the assumption that both instruction fetches and operand cycles are to a two clock memory Any time a long access is made time for the additional bus cycle s must be added to the overall execution time Wait states du e to slow external memory must be added to the access time for each bus cycle A typical application has a mixture of bus speeds program execution from an o...

Page 333: ... instruction N HN is the head time for instruction N TN is the tail time for instruction N min TN HM is the minimum of parameters TN and HM The number of cycles for the instruction CN above can include one or two effective address calculations in addition to the raw number in the cycles column In these cases calculate overall instruction time as if it were for multiple instructions using the follo...

Page 334: ...ntroduced to account for these free clocks on the bus On a two clock bus it is not necessary to adjust instruction timing to account for the potential extra prefetch The cycle times of the microsequencer and bus are matched and no additional benefit or penalty is obtained In the instruction execution time equations a zero should be used instead of a negative number Negative tails are used to adjus...

Page 335: ...eline is full at start 8 2 1 Timing Example 1 Execution Overlap Figure 8 4 illustrates execution overlap caused by the bus controller s completion of bus cycles while the sequencer is calculating the next effective address One clock is saved between instructions as that is the minimum time of the individual head and tail numbers CLOCK BUS CONTROLLER INSTRUCTION CONTROLLER 2 4 Instructions MOVE W A...

Page 336: ...e already in a data register CLOCK INSTRUCTION CONTROLLER EXECUTION TIME CLOCK Instructions MOVEQ CMP L BLE B MOVE L 7 D1 D1 00 NEXT 01 AO BLE B NOT TAKEN Figure 8 5 Example 2 Branch Taken 2 2 BUS 1PRE 3 PRE FETCH CONTROLLER FETCH INSTRUCTION CONTROLLER __ mmm MOVEO II O t T T JN I I I I 4 EXECUTION TIME MOVEO 7 D1 BLE B NOT TAKEN IIII I Figure 8 6 Example 2 Branch Not Taken CPU32 REFERENCE MANUAL...

Page 337: ...UCTION MOVE CONTROLLER TODD EXECUTION TIME Figure 8 7 Example 3 Branch Negative Tail Example 3 illustrates three different aspects of instruction time calculation The branch instruction does not attempt to prefetch beyond the minimum number of words needed for itself The negative tail allows execution to begin sooner than would a three word pipeline There is a one clock delay due to late arrival o...

Page 338: ... The outer number is the minimum number of cycles required for the instruction to complete Numbers within the parentheses represent the number of bus accesses performed by the instruction The first number is the number of operand read accesses performed by the instruction The second number is the number of instruction fetches performed by the instruction including all prefetches that keep the inst...

Page 339: ...1 Instruction Access x 2 Clocks Access 0 Writes x 2 ClockslWrite 6 Clocks of Bus Activity The number of internal clocks not overlapped by bus activity is 10 Clocks Total 6 Clocks Bus Activity 4 Internal Clocks Memory read requires two bus cycles at two clocks each This read time implied in the tail figure for the effective address cannot be overlapped with the instruction because the instruction h...

Page 340: ...ediate word effective address absolute word effective address address register indirect with displacement effective address conditional branches with word offsets bit operations LPSTOP TBL MOVEM MOVEC MOVES MOVEP MUL L OIV L CHK2 CMP2 and OBcc are not permitted to begin until the extension word has been in the instruction pipeline for at least one cycle This does not apply to long offsets or displ...

Page 341: ...Xm Sz Sc or d16 PC Xm Sz Sc 2 2 8 x 2 0 1 2 3 4 d32 An Xm Sz Sc or d32 PC Xm Sz Sc 1 3 9 X 3 0 1 2 3 4 X There is one bus cycle for by1e and word operands and two bus cycles for long operands For long bus cycles add two clocks to the tail and to the number of cycles NOTES 1 The read of the effective address and replacement fetches overlap the head of the operation by the amount specified in the ta...

Page 342: ... 7 0 3 0 1 4 An 1 0 4 0 1 0 4 Xm Sz Sc 4 0 6 0 1 0 2 4 An Xm Sz Sc 4 0 6 0 1 0 2 4 d16 An or d16 PC 1 1 5 0 2 0 1 3 4 d32 An or d32 PC 1 3 7 0 3 0 1 3 4 d16 An Xm or d16 PC Xm 2 0 6 0 2 0 3 4 d32 An Xm or d32 PC Xm 1 1 7 0 3 0 1 3 4 d16 An Xm Sz Sc or d16 PC Xm Sz Sc 2 0 6 0 2 0 2 3 4 d32 An Xm Sz Sc or d32 PC Xm Sz Sc 1 1 7 0 3 0 1 2 3 4 X There is one bus cycle for byte and word operands and two...

Page 343: ...n Am 1 1 5 0 1 x MOVE Rn Am 2 2 6 0 1 x MOVE Rn CEA 1 3 5 0 1 x MOVE FEA An 2 2 6 0 1 x MOVE FEA An 2 2 6 0 1 x MOVE FEA An 2 2 6 0 1 x MOVE CEA 2 2 6 0 1 x MOVE CEA FEA 2 2 6 0 1 x X There is one bus cycle for byte and word operands and two bus cycles for long operands For long bus cycles add two clocks to the tail and to the number of cycles An fetch effective address time must be added for this...

Page 344: ...4 MOVEP L d16 An On 1 2 19 4 2 0 MOVES Save CEA Rn 1 1 3 0 1 0 MOVES Op CEA Rn 7 1 11 X11 0 MOVES Save Rn CEA 1 1 3 0 1 0 MOVES Op Rn CEA 9 2 12 0 1 X MOVE USP An 0 0 2 0 1 0 MOVE An USP 0 0 2 0 1 0 SWAP On 4 0 6 0 1 0 X There is one bus cycle for byte and word operands and two bus cycles for long operands For long bus cycles add two clocks to the tail and to the number of cycles lEach bus cycle m...

Page 345: ...DD Dn FEA 0 3 5 0 1 x AND Dn Dm 0 0 2 0 1 0 AND FEA Dn 0 0 2 0 1 0 AND Dn FEA 0 3 5 0 1 x EOR Dn Dm 0 0 2 0 1 0 EOR Dn FEA 0 3 5 0 1 x OR Dn Dm 0 0 2 0 1 0 OR FEA Dn 0 0 2 0 1 0 OR Dn FEA 0 3 5 0 1 x SUB A Rn Rm 0 0 2 0 1 0 SUB A FEA Rn 0 0 2 0 1 0 SUB Dn FEA 0 3 5 0 1 x CMP A Rn Rm 0 0 2 0 1 0 CMP A FEA Rn 0 0 2 0 1 0 CMP2 Save FEA Rn 1 1 3 0 1 0 CMP2 Op FEA Rn 2 0 16 18 x 1 0 MUL S U W FEA Dn 0 ...

Page 346: ...clocks to the tail and to the number of cycles Maximum time certain data or mode combinations may execute faster su The execution time is identical for signed or unsigned operands These instructions have an additional save operation that other instructions do not have To calculate total instruction time calculate save e a and operation execution times then combine in the order shown using equation...

Page 347: ... number All timing data assumes two clock reads and writes MOTOROLA 8 20 Instruction Head Tall Cycles MOVEQ Dn 0 0 2 0 1 0 ADDQ Rn 0 0 2 0 1 0 ADDQ FEA 0 3 5 0 1 x SUBQ Rn 0 0 2 0 1 0 SUBQ FEA 0 3 5 0 1 Ix ADDI Rn 0 0 2 0 1 0 ADDI FEA 0 3 5 0 1 x ANDI Rn 0 0 2 0 1 0 ANDI FEA 0 3 5 0 1 x EORI Rn 0 0 2 0 1 0 EORI FEA 0 3 5 0 1 x ORI Rn 0 0 2 0 1 0 ORI FEA 0 3 5 0 1 x SUBI Rn 0 0 2 0 1 0 SUBI FEA 0 3...

Page 348: ...or these instructions The total number of clock cycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes Instruction Head ABCD ABCD SBCD SBCD ADDX ADDX SUBX SUBX CMPM CPU32 REFERENCE MANUAL Dn Dm 2 An Am 2 Dn Dm 2 An Am 2 Dn Dm 0 An Am 2 Dn Dm 0 An Am 2 An Am 1 INSTRUCTION EXECUTION TIMING...

Page 349: ...ds and writes MOTOROLA 8 22 Instruction Head Tall Cycles CLR On 0 0 2 0 1 0 CLR CEA 0 2 4 0 1 x NEG On 0 0 2 0 1 0 NEG FEA 0 3 5 0 1 x NEGX On 0 0 2 0 1 0 NEGX FEA 0 3 5 0 1 x NOT On 0 0 2 0 1 0 NOT FEA 0 3 5 0 1 x EXT On 0 0 2 0 1 0 NBCO On 2 0 4 0 1 0 NBCO FEA 0 2 6 0 1 1 Scc On 2 0 4 0 1 0 Scc CEA 2 2 6 0 1 1 TAS On 4 0 6 0 1 0 TAS CEA 1 0 10 0 1 1 TST FEA 0 0 2 0 1 0 X There is one bus cycle f...

Page 350: ...EA 0 2 6 0 1 1 ASd Dn Dm 2 0 0 1 0 ASd Dm 4 0 6 0 1 0 ASd FEA 0 2 6 0 1 1 ROd Dn Dm 2 0 0 1 0 ROd Dm 4 0 6 0 1 0 ROd FEA 0 2 6 0 1 1 ROXd Dn Dm 2 0 0 1 0 ROXd Dm 2 0 0 1 0 ROXd FEA 0 2 6 0 1 1 NOTES 1 Head and cycle times can be calculated as follows Max 3 n 4 mod n 4 mod n 4 mod n 4 1 2 6 or derived from the following table 2 Head and cycle times are calculated as follows count 63 max 3 n mod n 1...

Page 351: ...a assumes two clock reads and writes MOTOROLA 8 24 Instruction Head Tall Cycles BCHG On 2 0 6 0 2 0 BCHG On Om 4 0 6 0 1 0 BCHG FEA 1 2 8 0 2 1 BCHG On FEA 2 2 8 0 1 1 BClR On 2 0 6 0 2 0 BClR On Om 4 0 6 0 1 0 BClR FEA 1 2 8 0 2 1 BClR On FEA 2 2 8 0 1 1 BSET On 2 0 6 0 2 0 BSET On Om 4 0 6 0 1 0 BSET FEA 1 2 8 0 2 1 BSET On FEA 2 2 8 0 1 1 BTST On 2 0 4 0 2 0 BTST On Om 2 0 4 0 1 0 BTST FEA 1 0 ...

Page 352: ...ycles is outside the parentheses The numbers inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes Instruction Head Bcc Bee B Bcc W Bee L DBee DBee DBee DBee DBee DBee In loop mode CPU32 REFERENCE MANUAL taken 2 not taken 2 not taken 0 not taken 0 T not taken 1 F 1 not taken 2 F not 1 taken 6 T not taken 4 F 1 not taken 6 F not 1 t...

Page 353: ... 8 0 1 0 CHK FEA Dn ex 2 2 42 2 2 6 CHK2 Save FEA Dn no ex 1 1 3 0 1 0 CHK2 Op FEA Dn no ex 2 0 18 XlO 0 CHK2 Save FEA Dn ex 1 1 3 0 1 0 CHK2 Op FEA Dn ex 2 2 52 x 2 1 6 JMP CEA 0 2 6 0 2 0 JSR CEA 3 2 13 0 2 2 LEA CEA An 0 0 2 0 1 0 LlNK W An 2 0 10 0 2 2 LlNK L An 0 0 10 0 3 2 Nap 0 0 2 0 1 0 PEA CEA 0 0 8 0 1 2 RID 1 2 12 2 2 0 RlR 1 2 14 3 2 0 RTS 1 2 12 2 2 0 UNLK An 1 0 9 2 1 0 X There is on...

Page 354: ... 2 6 Trace 0 2 36 2 2 6 TRAP 4 2 29 2 2 4 ILLEGAL 0 2 25 2 2 4 A line 0 2 25 2 2 4 F Iine First word illegal 0 2 25 2 2 4 F Iine Second word illegal ea Rn 1 2 31 2 3 4 F Iine Second word illegal ea f Rn Save 1 1 3 0 1 0 F Iine Second word illegal ea f Rn Op 4 2 29 2 2 4 Privileged 0 2 25 2 2 4 TRAPcc trap 2 2 38 2 2 6 TRAPcc no trap 2 0 4 0 1 0 TRAPcc W trap 2 2 38 2 2 6 TRAPcc W no trap 0 0 4 0 2...

Page 355: ... inside parentheses r p w are included in the total clock cycle number All timing data assumes two clock reads and writes MOTOROLA 8 28 Instruction Head Tail Cycles BERR on instruction 0 2 58 2 2 12 BERR on exception 0 2 48 212112 RTE four word frame 1 2 24 4 2 0 RTE six word frame 1 2 26 4 2 0 RTE BERR on instruction 1 2 50 12 12 y RTE BERR on four word frame 1 2 66 10 2 4 RTE BERR on six word fr...

Page 356: ...Bus Error Detection Instruction Continuation Bus Error Detection Instruction Restart Bus Error Detection Instruction Continuation Coprocessor Interface MC68000 MC68010 CPU32 MC68020 Emulated in Software Emulated in Software Emulated in Software In Microcode Word Long Word Data Alignment MC68000 MC68010 CPU32 MC68020 Word Long Word Data Instructions and Stack Must Be Word Aligned Word Long Word Dat...

Page 357: ...1fTO S M 10 11 12 XlN ZN C Function Code Address Space MC68000 MC68010 CPU32 MC68020 FCO FC2 is Interrupt Acknowledge Only FCO FC2 7 is CPU Space FCO FC2 7 is CPU Space FCO FC2 7 is CPU Space Indivisible Bus Cycles MC68000 MC68010 CPU32 MC68020 Stack Frames MC68000 MC68010 CPU32 MC68020 MOTOROLA A 2 Use AS Signal Use AS Signal Use RMC Signal Use RMC Signal Supports Original Set Supports Formats 0 ...

Page 358: ...g CMP2 New Instruction cp Coprocessor Instructions DIVS DIVU Supports 32 Bit and 64 Bit Operations EXTB Supports 8 Bit Extend to 32 Bits LINK Supports 32 Bit Displacement LPSTOP New Instruction MOVEC Supports New Control Registers MULSIMULU Supports 32 Bit Operands and 64 Bit Results PACK New Instruction RTM New Instruction TBLSN TBLUN New Instruction TBLS TBLU TST Supports Program Counter Relativ...

Page 359: ...d An Xn SCALE 0 0 Base Displacement Memory Indirect with Postincrement bd An Xn Od 0 Memory Indirect with Predecrement bd An Xn Od 0 Absolute Short xxx W 0 0 0 Absolute Long xxx L 0 0 0 Program Counter Indirect with d16 PC 0 0 0 Displacement Program Counter Indirect with Index ds PC Xn 0 0 0 8 Bit Displacement Program Counter Indirect with Index bd PC Xn SCALE 0 0 Base Displacement Immediate data ...

Page 360: ... 4 10 Assignments Exception Vector 6 2 Asynchronous Bus Operation See appropriate user s manual 8 Background Debug Mode 7 3 Commands Execution 7 6 Format 7 14 Sequence Diagrams 7 16 Sequence Example 7 17 CPU32 REFERENCE MANUAL INDEX INDEX Set 7 14 Summary 7 17ff Enabling 7 4 Entering 7 5 Returning from 7 8 Sources 7 4 Registers 7 6 Serial Interface 7 8 BGND Instruction 7 5 Binary Coded Decimal Ope...

Page 361: ...Sequence 6 3 Reset 6 6 Related Instructions and Operations 8 24 Return from 6 16 Stack Frame 6 4 Trace 6 13 Types 6 3 Unimplemented Instruction 6 11 Vectors 6 1 Execution Time Calculations 8 6ff Execution Overlap 8 8 MOTOROLA 2 INDEX F Faults Correcting 6 22 Type I via Software 6 23 Type I via RTE 6 23 Type II via RTE 6 24 Type III via Software 6 24 Type III via Conversion and Restart 6 25 Type II...

Page 362: ...ect Addressing 3 5ff Organization 2 7 Virtual 1 2 Microbus Controller 8 4 Microsequencer 8 1 Model Programming 2 1 Move Instruction Timing 8 14 Move Instruction Special Purpose Timing 8 15 Multiple Exceptions 6 4 N CPU32 REFERENCE MANUAL INDEX Negative Tails 8 7 Organization in Memory 2 7 Notation Instruction Set 4 4 Notation Conventions Addressing 3 2 Normal Processing State 5 1 0 Opcode Tracking...

Page 363: ...ce Interpolation 4 195 4 203 System Control Instructions 4 15 Stack 3 20 Synchronization Pipeline with NOP 4 203 MOTOROLA 4 INDEX T Table Lookup and Interpolation 4 195 Examples Standard Usage 4 196 Compressed Table 4 197 8 Bit Independent Variable 4 199 Maintaining Precision 4 201 Surface Interpolations 4 203 Instruction Using the 4 192 Tests Condition 4 17 Timing Examples Execution Overlap 8 8 B...

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Page 366: ...Architecture Summary III Data Organization and Addressing Capabilities lEI Instruction Set III Processing States II Exception Processing II Development Support Instruction Execution Timing M68000 Family Summary III ...

Page 367: ...anization and Addressing Capabilities II Instruction Set III Processing States III Exception Processing Development Support III Instruction Execution Timing III M68000 Family Summary A24846 3 PRINTED IN USA 12 90 EVANS PRESS EMTR 1376 40 000 MCU YGACAA ...