Multi-Processor Interrupt Controller (MPIC)
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Multi-Processor Interrupt Controller (MPIC)
The MPIC is a multi-processor structured intelligent interrupt controller.
MPIC Features:
❏
MPIC programming model
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Supports two processors
❏
Supports 16 external interrupts
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Supports 15 programmable Interrupt & Processor Task priority
levels
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Supports the connection of an external 8259 for ISA/AT
compatibility
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Distributed interrupt delivery for external I/O interrupts
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Direct/Multicast interrupt delivery for Interprocessor and timer
interrupts
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Four Interprocessor Interrupt sources
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Four timers
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Processor initialization control
Architecture
The PCI Slave of the PHB implements two address decoders for placing
the MPIC
registers in PCI IO or PCI Memory space. Access to these
registers requires PPC and PCI bus mastership. These accesses include
interrupt and timer initialization and interrupt vector reads.
The MPIC receives interrupt inputs from 16 external sources, four
interprocessor sources, four timer sources, and one Hawk internal error
interrupt source. The externally sourced interrupts 1 through 15 have two
modes of activation; low level or active high positive edge. External
interrupt 0 can be either level or edge activated with either polarity. The
Hawk internal error interrupt request is an active low level sensitive
interrupt.
The Interprocessor and timers interrupts are event activated.
Summary of Contents for MVME5100 Series
Page 1: ...MVME5100 Single Board Computer Programmer s Reference Guide V5100A PG2 September 2001 Edition ...
Page 16: ...xvi ...
Page 20: ...xx ...
Page 28: ...xxviii ...
Page 62: ...1 34 Computer Group Literature Center Web Site Product Data and Memory Maps 1 ...
Page 278: ...3 88 Computer Group Literature Center Web Site System Memory Controller SMC 3 ...
Page 288: ...4 10 Computer Group Literature Center Web Site Hawk Programming Details 4 ...
Page 320: ...Index IN 12 Computer Group Literature Center Web Site I N D E X ...