Chapter 4
Programming
4-54
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National Instruments Corporation
Make sure that the same logical channel is not assigned to more than one
resource. Also, the same physical channel number should not be assigned
to more than one logical channel.
DMA requests are generated when all of the above mentioned
initializations are done and when the source is programmed appropriately.
For analog input, the AIFREQ signal from the DAQ-STC is used as the
DMA source. For more information, see Chapter 2 of the DAQ-STC
Technical Reference Manual. By using the
FIFO_Request_Selection
function, you can generate DMA requests based on any of the following
conditions:
•
FIFO not empty
•
FIFO half-full
•
FIFO full
•
FIFO half-full until FIFO is empty
For analog output, the AOFREQ signal from the DAQ-STC is used as the
DMA source. By using the
AO_FIFO
function you can generate DMA
requests based on any of the following conditions:
•
FIFO empty
•
FIFO less than half-full
•
FIFO not full
•
Assert on FIFO half-full and deassert on FIFO full
For general-purpose counter/timers, an interrupt is produced in buffered
modes, such as the buffered event counting, the buffered period
measurement, and so on. The secondary bank of interrupts in the DAQ-STC
is used for generating DMA requests for the general-purpose
counter/timers.
Single Channel Versus Dual Channel DMA
If single channel DMA is used, the DMA controller uses a single channel
to transfer data. The DMA controller writes to or reads from a buffer in
memory. The maximum number of bytes that can be transferred vary from
platform to platform, with 128 kbytes in ISA to 16 MB in EISA. Regardless
of the size, after the maximum bytes have been transferred, the DMA
controller issues a TC which generates an interrupt, if the board is
programmed for DMA. Usually, the interrupt latency is long enough so
that, by the time you reprogram your DMA controller, some data is lost.
This affects sustained throughput.
Summary of Contents for AT-AI-16XE-10
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