Universal Serial Bus Interface
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
24-13
provides bit descriptions for the HCCPARAMS register.
Address MBAR2 + 0x708
Access: User read
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
EECP
IST
ASP
PFL
ADC
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
Figure 24-11. Host Control Capability Parameters (HCCPARAMS) Register
Table 24-12. Host Control Capability Parameters (HCCPARAMS) Register Field Descriptions
Field
Description
31–16 Reserved.
15–8
EECP
EHCI Extended Capabilities Pointer. This optional field indicates the existence of a capabilities list. A value of 0x00
indicates no extended capabilities are implemented. A non-zero value in this register indicates the offset in PCI
configuration space of the first EHCI extended capability. The pointer value must be 0x40 or greater if implemented to
maintain the consistency of the PCI header defined for this class of device.
This field is always 0.
7–4
IST
Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller,
where the software can reliably update the isochronous schedule. When bit [7] is zero, the value of the least significant
3 bits indicates the number of microframes a host controller can hold a set of isochronous data structures (one or more)
before flushing the state. When bit [7] is a one, then the host software assumes the host controller may cache an
isochronous data structure for an entire frame.
This field is always 0.
3
Reserved.
2
ASP
Asynchronous Schedule Park Capability. This bit indicates if the host controller supports the park feature for high-speed
queue heads in the Asynchronous Schedule. The feature can be disabled or enabled and set to a specific level by using
the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD
register.
This field is always 1(park feature supported).
1
PFL
Programmable Frame List Flag. This bit indicates that the system software can specify and use a frame list length less
that 1024 elements. Frame list size is configured via the USBCMD register Frame List Size field. The frame list must
always be aligned on a 4K page boundary. This requirement ensures that the frame list is always physically contiguous.
This field is always 1.
0
ADC
64-bit Addressing Capability. This field is always 0; 64-bit addressing is not supported.
0 Data structures use 32-bit address memory pointers
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...
