R01UH0823EJ0100 Rev.1.00
Page 701 of 1823
Jul 31, 2019
RX23W Group
25. 16-Bit Timer Pulse Unit (TPUa)
25.3.6
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected by the settings for channels
1, 2, 4, and 5, and TPUm.TCNT is incremented/decremented accordingly.
When phase counting mode is set, an external clock is selected as the count clock and TCNT operates as an up-/down-
counter regardless of the setting of the TPSC[2:0] bits and CKEG[1:0] bits in TPUm.TCR. However, the lower 2 bits of
the CCLR[2:0] bits in TPUm.TCR and the functions of TPUm.TIORH, TPUm.TIORL, TPUm.TIOR, TPUm.TIER, and
TPUm.TGRy are valid, and therefore input capture/compare match and interrupt functions are available.
When an overflow occurs while TCNT is counting up, a TCIV interrupt request is generated; when an underflow occurs
while TCNT is counting down, a TCIU interrupt request is generated. The TCFD bit in TPUm.TSR is the count direction
flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down.
In phase counting mode, the external clock pins TCLKA, TCLKB, TCLKC, and TCLKD can be used as 2-phase encoder
pulse input.
lists the correspondence between external clock pins and channels.
(1) Example of Phase Counting Mode Setting Procedure
shows an example of the phase counting mode setting procedure.
Figure 25.24
Example of Phase Counting Mode Setting Procedure
Table 25.23
Clock Input Pins in Phase Counting Mode
Channel
External Clock Pins
A-Phase
B-Phase
When TPU1 or TPU5 is set to phase counting mode
TCLKA
TCLKB
When TPU2 or TPU4 is set to phase counting mode
TCLKC
TCLKD
Select phase counting mode
Phase counting mode
Start counting
<Phase counting mode>
[1]
[2]
[1] Select phase counting mode with the MD[3:0] bits in
TMDR.
[2] Set the TPU.TSTR.CSTj bit (j = 1, 2, 4, 5) to 1 to start
the counter operation.
