Rohm LAPIS ML22594 MB Series, Manual

Page 1: ...ch phrase HQ ADPCM 8 bit non linear PCM 8 bit PCM 16 bit PCM Sampling frequency Can be specified for each phrase 12 0 24 0 48 0 kHz 8 0 16 0 32 0 kHz 6 4 12 8 25 6 kHz Built in low pass filter and 16 bit D A converter Built in speaker driver amplifier 1 0 W 8Ω at DVDD 5 V with over current detectible function for Speaker pins External analog voice input built in analog mixing function CPU command ...

Page 2: ...12 0 12 8 16 0 24 0 25 6 32 0 48 0 Clock frequency 4 096 MHz has a crystal oscillator circuit built in D A converter 16 bit voltage type Low pass filter FIR interpolation filter High pass interpolation Speaker driving amplifier Built in 1 0 W 8Ω DVDD 5 V Over current detectible function for Speaker Pins No Yes Simultaneous sound production function mixing function 4 channel Edit ROM Yes Volume con...

Page 3: ...FEDL22594 06 ML22594 XXX 3 73 1 Continuous playback as shown below is possible Playback method 8 bit straight PCM 8 bit non linear PCM 16 bit straight PCM 1 phrase 1 phrase No silence interval ...

Page 4: ...Diagram of ML22594 xxx Timing Controller I O Interface Address Controller SPM RESETB CSB SCK SI SO CBUSYB STATUS ERR DIPH OSC XTB XT SPVDD SPGND PLL PCM Synthesizer LPF CVOL 16bit DAC SP AMP AVOL SPP AIN DVDD DGND VDDL SG TESTI1 Cmd Analyzer 6Mbits MASKROM Serial ROM Interface ESCK ESO ESI IOV DD ECSB FLW ...

Page 5: ...594 xxx 30 Pin Plastic SSOP NC Unused pin AIN SG NC DVDD DGND VDDL DIPH STATUS ERR CSB SCK SI SO CBUSYB DGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SPVDD SPGND SPP SPM ESI ESO ESCK ECSB TESTI1 FLW RESETB IOVDD DVDD XT XTB 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ...

Page 6: ... LSI on the falling edges of the SCK clock pulses and a status signal is output from the SO pin on the rising edges of the SCK clock pulses digital 0 8 STATUS O Positive Channel status output pin Outputs the BUSYB or NCR signal for each channel by inputting the OUTSTAT command digital 1 9 ERR O Positive Error output pin Outputs a H level if an error occurs digital 0 10 CSB I Negative Chip select p...

Page 7: ...a L level to this pin After the power supply voltage is stabilized drive this pin at a H level This pin has a pull up resistor built in digital 0 21 FLW I Positive External ROM interface disenable pin When a H level is inputted the external ROM interface is disenable L level is inputted the external ROM interface is enable Has a pull down resistor built in digital 0 22 TESTI1 I Negative Used as ei...

Page 8: ...S Applies to all pins except SPM SPP VDDL and VDDR 10 mA Applies to SPM and SPP pins 500 mA Applies to VDDL and VDDR pins 50 mA Storage temperature TSTG 55 to 150 C RECOMMENDED OPERATING CONDITIONS DGND SPGND 0 V Parameter Symbol Condition Range Unit DVDD SPVDD Power supply voltage DVDD SPVDD 4 5 to 5 5 V IOVDD Power supply voltage IOVDD 2 7 to 5 5 1 V Operating temperature Top 40 to 105 C Master ...

Page 9: ...IL2 VIL DGND 20 5 0 0 8 µA L input current 3 13 IIL3 VIL DGND 400 100 20 µA Supply current during playback 1 IDD1 fOSC 4 096 MHz fs 48kHz f 1kHz When 16bitPCM Playback No output load 54 15 mA 1 16 Supply current during playback 2 14 IDD2 fOSC 4 096 MHz fs 48kHz f 1kHz When 16bitPCM Playback using External ROM No output load 50 15 mA 5 16 Supply current during playback 3 IDD3 fOSC 4 096 MHz During ...

Page 10: ...E output load resistance RLA At SPGND10kΩ load 10 kΩ LINE output voltage range VAO At SPGND10kΩ load SPVDD 6 SPVDD 5 6 V SG output voltage VSG 0 95x SPVDD 2 SPVDD 2 1 05x SPVDD 2 V SG output resistance RSG 57 96 135 kΩ SPM SPP output load resistance RLSP 6 8 Ω Speaker amplifier output power PSPO SPVDD 5 0V f 1 kHz RSPO 8Ω THD 10 800 1000 mW Output offset voltage between SPM and SPP with no signal ...

Page 11: ...L level output time tPUP 4 096 MHz At external clock input 4 ms At AMODE command input CBUSYB L level output time 3 tPUPA1 4 096 MHz At external clock input POP 0 DAEN 0 1 or SPEN 0 1 39 41 43 ms At AMODE command input CBUSYB L level output time tPUPA2 4 096 MHz At external clock input POP 1 DAEN 0 1 SPEN 0 72 74 76 ms At AMODE command input CBUSYB L level output time tPUPA3 4 096 MHz At external ...

Page 12: ...USYB L level output time 3 4 tCB3 fOSC 4 096 MHz 200 µs Note Output pin load capacitance 45 pF Max 1 Applies to cases where a command is input except after the PUP PDWN PLAY START or AMODE command input 2 Applies to cases where the PLAY or START command is input 3 When FAD3 0 is initial value 8h 4 Applies to cases where the STOP command is input ...

Page 13: ... rise tDBSY1 DIPH L 90 ns CBUSYB output delay time from SCK fall tDBSY2 DIPH H 90 ns Note Output pin load capacitance 45 pF Max AC Characteristics 3 External ROM serial interface DVDD SPVDD 4 5 to 5 5 V IOVDD 2 7 to 5 5 V DGND SPGND 0 V Ta 40 to 105 C Parameter Symbol Condition Min Typ Max Unit ESCK input enable time from ECSB fall edge tECSS fOSC 4 096 MHz 50 ns ESCK input hold time from ECSB ris...

Page 14: ...Serial Interface Data Timing CSB SCK SI VIH VIL VIL VIH VIL VIH tESCK tDIS1 tDIH1 tSCKH tSCKL tCSH CBUSYB tDBSY1 VOL VOH SO VIL VIH tDOZ tDOD1 CSB SCK SI VIH VIL VIL VIH VIL VIH tESCK tDIS2 tDIH2 tSCKL tSCKH tCSH CBUSYB tDBSY2 VOL VOH SO VIL VIH tDOZ ECSB ESCK ESI VIH VIL VIL VIH VIL VIH tECSS tEDIS tEDIH tESCKH tESCKL tECSH ESO tEDOD VOL VOH tESCKF ...

Page 15: ... Be sure to power on IOVDD after DVDD SPVDD When IOVDD isn t used it is possible that it is fixed in 0V Be sure to set L level the RESETB pin before the first command input DVDD 5V IOVDD 3 3V 10 90 90 SPVDD IOVDD Status Be sure to power shut down DVDD SPVDD after IOVDD When IOVDD isn t used it is possible that it is fixed in 0V DVDD 5V Power down 3 3V 5V ...

Page 16: ...16 73 Reset Input Timing Note The same timing applies in cases where the Reset signal is input during waiting for command tRST RESETB Status Power down Playing XT XTB Oscillating Oscillation stopped VDDL SG GND SPM GND SPP Hi Z ...

Page 17: ...g reset processing SCK SI NCRn BUSYBn Power down XT XTB Oscillating Oscillation stopped VOH VOL Awaiting command internal internal VOH VOL CBUSYB VOH VOL CSB Status Command is being processed Power down SCK SI NCRn BUSYBn Awaiting command XT XTB Oscillating Oscillation stopped VOH VOL internal internal VOH VOL tPD CBUSYB ...

Page 18: ...processed Playing SCK SI NCRn BUSYBn Command standby SPM 1 2VDD SPP 1 2VDD VOH VOL Address is being controlled Awaiting command Awaiting command 1 PLAY command 1 st byte PLAY command 2 nd byte internal internal VOH VOL CBUSYB tCB1 tCB2 VOH VOL CSB Status Awaiting command SCK SI NCRn BUSYBn SPM 1 2VDD SPP 1 2VDD VOH VOL Playing STOP command internal internal VOH VOL CBUSYB tCB3 Command is being pro...

Page 19: ...ess is being controlled Awaiting command Playing phrase 2 tCB1 tcm internal internal VOH VOL CBUSYB tCB2 tCB1 PLAY command 1 st byte PLAY command 2 nd byte PLAY command 2 nd byte VOH VOL CSB Status Playing SCK SI NCRn BUSYBn SPM 1 2VDD SPP 1 2VDD Address is being controlled Awaiting command Silence is being inserted tCB1 Playing Waiting for silence insertion to be finished tCB1 tcm VOH VOL CBUSYB ...

Page 20: ...Awaiting command Awaiting command PLAY command 2nd byte SLOOP command Playing Address is being controlled CLOOP command tINT Command is being processed VIH VIL VOH VOL CBUSYB tCB2 tcm internal internal VOH VOL CSB Status Awaiting command SCK SI NCRn BUSYBn Command is being processed tCB1 Awaiting command CVOL command 1st byte VOH VOL VOH VOL CBUSYB internal internal tCB1 Command is being processed...

Page 21: ... ROM interface at FLW rise External ROM interface at FLW fall VOH VOL FLW Status Hi Z PSCK PSI Output VOH VOL VOH VOL tEFLH PCSB VIH VIL Hi Z Hi Z Hi Z VOH VOL FLW Status Output PSCK PSI Hi Z VOH VOL VOH VOL tEFHL PCSB VIH VIL Hi Z Hi Z Hi Z ...

Page 22: ...en the DIPH pin is at a H level the data input through the SI pin is shifted into the LSI on the falling edges of the SCK clock pulses and a status signal is output from the SO pin on the rising edges of the SCK clock pulses It is possible to input commands even with the CSB pin tied to a L level However if unexpected pulses caused by noise etc are induced through the SCK pin SCK clock pulses are ...

Page 23: ...omes valid only when the data input first matches the data input second After the first data input if a data mismatch occurs when the second data is input a H level is output from the ERR pin An error if occurred can be cleared by the ERCL command VOH VOL CSB Status Command is being processed Playing SCK SI NCRn BUSYBn Awaiting command SPM 1 2VDD SPP 1 2VDD VOH VOL Address is being controlled Awai...

Page 24: ...ht PCM algorithm Key feature of each algorithm is described in the table below Voice synthesis algorithm Feature HQ ADPCM Algorithm that enables high sound quality and high compression which have been achieved by the improved 4 bit ADPCM that uses variable bit length coding 8 bit Nonlinear PCM Algorithm that plays back mid range of waveform as 10 bit equivalent voice quality 8 bit PCM Normal 8 bit...

Page 25: ...d The ROM data is created using a dedicated tool Playback Time and Memory Capacity The playback time depends on the memory capacity sampling frequency and playback method The equation showing the relationship is given below The equation below gives the playback time when the edit ROM function is not used Example Let the sampling frequency be 16 kHz and HQ ADPCM algorithm Then the playback time is ...

Page 26: ...depends on the memory capacity only Silence insertion 20 to 1024 ms Using the edit ROM function enables an effective use of the memory capacity of voice ROM Below is an example of the ROM configuration in the case of using the edit ROM function Phrase 1 Phrase 2 Phrase 3 Phrase 4 A D A C E B E C Phrase 5 D D D B A D B E B D Silence A B C D E Address control area Editing area Examples of Phrases Us...

Page 27: ...roup other than the selected sampling frequency group then the playback will not be of constant speed some times faster and at other times slower The available sampling groups for channel mixing by a different sampling frequency are listed below 8 0 kHz 16 0 Hz 32 0 kHz Group 1 12 0 kHz 24 0 kHz 48 kHz Group 2 6 4 kHz 12 8 kHz 25 6 kHz Group 3 Figures below show cases where a phrase is played at a...

Page 28: ...RR pin becomes H 1 After setting power down by the AMODE command do power up by the AMODE command 2 After detect a short error when input ERCL command without power down operation of speaker amplifier by the AMODE command over current detectible function for Speaker pins HiZ ERR Serial I F PUP SPP SPVDD SPGND SPM SPVDD SPGND analog powerdown speaker powerdown analog powerup speaker powerup analog ...

Page 29: ...e 2nd byte to specify volume AV5 AV4 AV3 AV2 AV1 AV0 FAD 0 0 0 0 1 1 0 0 Sets the fade in time in cases where the speaker amplifier is enabled by the AMODE command 0 0 0 0 FAD3 FAD2 FAD1 FAD0 PDWN 0 0 1 0 0 0 0 0 Shifts the device from a command wait state to a power down state FADR 0 0 1 1 C1 C0 F9 F8 Playback phrase specification command Can be specified for each channel F7 F6 F5 F4 F3 F2 F1 F0 ...

Page 30: ...lly Can be specified for each channel CVOL 1 0 1 0 CH3 CH2 CH1 CH0 Volume setting command Use the data of the 2nd byte to specify volume Can be specified for each channel CV4 CV3 CV2 CV1 CV0 RDSTAT 1 0 1 1 0 0 0 ERR Status serial read command This command reads the command status and the status of the fail safe function for each channel OUTSTAT 1 1 0 0 0 BUSY NCR C1 C0 Status output command This c...

Page 31: ...bit is used to set the two time command input mode When set to 1 the command input thereafter will be processed in two time command input mode and becomes valid only when the first data input matches the second one WCM Two time command input mode 0 No initial value 1 Yes The regulator starts operating after the PUP command is entered Any command will be ignored if entered while oscillation is stab...

Page 32: ...the STOP command during the AMODE command is being proccessed CBUSYB L Input the AMODE command for analog section into the power down state before the PDWN command is input The HPF1 HPF0 bits set the cut off frequency of the HPF HPF1 HPF0 Cut off frequency 0 0 Off initial value 0 1 200 Hz 1 0 300 Hz 1 1 400 Hz The POP bit specifies whether to suppress generation of pop noise If the bit is 0 no pop...

Page 33: ...aiting command VOH VOL Command is being processed Awaiting command AMODE command 1st byte AMODE command 2nd byte LINE output GND SPM GND 1 2SPVDD SPP Hi Z 1 2SPVDD VOH VOL CBUSYB tCB1 tPUPA1 internal internal internal 1 2DVDD VOH VOL CSB SCK SI NCR BUSYB VOH VOL AMODE command 1st byte AMODE command 2nd byte SPP VOH VOL CBUSYB tCB1 tPUPA2 GND 1 2DVDD internal internal LINE output Status Command is ...

Page 34: ... byte AMODE command 2nd byte SPP VOH VOL CBUSYB tCB1 tPUPA3 GND 1 2DVDD internal internal LINE output Status Command is being processed Awaiting command Awaiting command Awaiting command Command is being processed VOH VOL CSB SCK SI NCR internal BUSYB internal VOH VOL LINE output SPM SPP VOH VOL CBUSYB tCB1 tPDA1 GND 1 2DVDD GND 1 2SPVDD Hi Z 1 2SPVDD Status Command is being processed Awaiting com...

Page 35: ...SYB VOH VOL SPP VOH VOL CBUSYB tCB1 tPDA2 GND 1 2DVDD internal internal LINE output AMODE command 1st byte AMODE command 2nd byte Status Command is being processed Awaiting command Awaiting command Awaiting command Command is being processed POP noise suppressed VOH VOL CSB SCK SI NCR BUSYB VOH VOL SPP VOH VOL CBUSYB tCB1 tPDA3 GND 1 2DVDD internal internal LINE output AMODE command 1st byte AMODE...

Page 36: ...nitial value 1 Power up state The SPEN bit takes power up and power down control of the speaker section When the SPEN bit 0 the SPP pin is configured as a LINE output SPEN Status of the speaker section 0 Power down state initial value 1 Power up state Relationship between DAEN SPEN and POP signals and the analog section DAEN SPEN POP Mode Status 0 0 0 At speaker output Power down initial value At ...

Page 37: ...mand is input the value set by the AVOL command is initialized 0 dB AV5 0 Volume AV5 0 Volume 3F 12dB 1F 8 0 3E 11 5 1E 9 0 3D 11 0 1D 10 0 3C 10 5 1C 11 0 3B 10 0 1B 12 0 3A 9 5 1A 13 0 39 9 0 19 14 0 38 8 5 18 16 0 37 8 0 17 18 0 36 7 5 16 20 0 35 7 0 15 22 0 34 6 5 14 24 0 33 6 0 11 26 0 32 5 5 12 28 0 31 5 0 11 30 0 30 4 5 10 32 0 2F 4 0 0F 34 0 2E 3 5 0E OFF 2D 3 0 0D OFF 2C 2 5 0C OFF 2B 2 0...

Page 38: ... for the speaker amplifier The fade in time cna be adjusted through 16 levels as shown in the table below The initial value after reset is 298 µs When the PUP command is input the value set by the FAD command is initialized 298 µs FAD3 0 Fade in time µs F 442 E 422 D 401 C 381 B 360 A 340 9 319 8 298 initial value 7 278 6 257 5 237 4 216 3 195 2 175 1 154 0 134 ...

Page 39: ...nd then input the PLAY command Oscillation stops after a lapse of command processing time after the PDWN command is input The regulator stops operation after a lapse of command processing time after the PDWN command is input At this time the SPM output of the speaker amplifier goes into a Hi Z state to prevent generation of pop noise Initial stauts at reset input and status during power down The s...

Page 40: ...art playback Since it is possible to specify a playback phrase F9 F0 at the time of creating a ROM that stores voice data specify the phrase that was specified when the ROM was created Number of phrase Internal ROM and External ROM Number of phrase F9 F0 Internal ROM 512 000h 1FFh External ROM 512 200h 3FFh Channel settings C1 C0 Channel 0 0 Channel 0 0 1 Channel 1 1 0 Channel 2 1 1 Channel 3 The ...

Page 41: ...rom the ROM the address information of the phrase to be played Thereafter playback operation starts the playback is performed up to the specified ROM address and then the playback terminates automatically The NCR signal is at a L level during address control and goes H when the address control is finished and playback starts When the NCR signal on the target channel goes H it is possible to input ...

Page 42: ... the diagram above if performing continuous playback input the PLAY command for the second phrase within 10 ms tcm after the NCR signal on the target channel goes H Input the following PLAY command after checking that playback is completed by the RDSTAT command when it is not continuous playback CSB SCK SI NCR BUSYB SPM 1 2VDD SPP 1 2VDD tcm CBUSYB internal internal PLAY command 2nd byte PLAY comm...

Page 43: ...and with each NCR set to a H level The figure below shows the timing when starting playback on channel 00 and channel 1 simultaneously Channel settings Channel CH0 Setting this bit to 1 starts playback on channel 0 CH1 Setting this bit to 1 starts playback on channel 1 CH2 Setting this bit to 1 starts playback on channel 2 CH3 Setting this bit to 1 starts playback on channel 3 Be sure to set the c...

Page 44: ...forming continuous playback input the START command for the second phrase within 10 ms tcm after the NCR signal on the target channel goes H Input the following START command after checking that playback is completed by the RDSTAT command when it is not continuous playback SPM 1 2VDD SPP 1 2VDD Status Playing phrase 1 Address is being controlled Awaiting command Playing phrase 2 CSB SCK SI NCR BUS...

Page 45: ...t the STOP command regardless of the status of NCR during playback a prescribed command interval time needs taking Channel settings Channel CH0 Setting this bit to 1 stops playback on channel 0 CH1 Setting this bit to 1 stops playback on channel 1 CH2 Setting this bit to 1 stops playback on channel 2 CH3 Setting this bit to 1 stops playback on channel 3 Be sure to set the channel setting bits CH0 ...

Page 46: ...silence on channel 2 CH3 Setting this bit to 1 inserts a silence on channel 3 Be sure to set the channel setting bits CH0 CH3 As the silence length M7 M0 a value between 20 ms and 1024 ms can be set at 4 ms intervals 252 steps in total The equation to set the silence time length is shown below The silence length M7 M0 must be set to 04h or higher tmu 2 7 M7 2 6 M6 2 5 M5 2 4 M4 2 3 M3 2 2 M2 2 1 M...

Page 47: ...PLAY command in order to play phrase 1 After the PLAY command input the NCR signal once again goes to a L level and the device enters a state waiting for the termination of silence playback When the silence playback is terminated and then the phrase 1 playback starts the NCR signal goes H and the device enters a state where it is possible to input the next PLAY or MUON command The BUSYB signal rem...

Page 48: ...t the current phrase is repeatedly played until the repeat playback setting is released by the SLOOP command or until playback is stopped by the STOP command In the case of a phrase that was edited using the edit function the edited phrase is repeatedly played Following shows the SLOOP command input timing Effective Range of SLOOP Command Input The SLOOP command is only enabled during playback Aft...

Page 49: ...f the NCR signal during playback but a prescribed command interval needs taking Channel settings Channel CH0 Setting this bit to 1 releases repeat playback on channel 0 CH1 Setting this bit to 1 releases repeat playback on channel 1 CH2 Setting this bit to 1 releases repeat playback on channel 2 CH3 Setting this bit to 1 releases repeat playback on channel 3 Be sure to set the channel setting bits...

Page 50: ...t to 1 sets the volume on channel 0 CH1 Setting this bit to 1 sets the volume on channel 1 CH2 Setting this bit to 1 sets the volume on channel 2 CH3 Setting this bit to 1 sets the volume on channel 3 Be sure to set the channel setting bits CH0 CH3 The command enables 32 level adjustment of volume as shown in the table below The initial value after reset release is set to 0 dB Upon reset release o...

Page 51: ...fe function If the ERR bit is set to 0 the following status will be read Output bit D7 D6 D5 D4 D3 D2 D1 D0 Output data BUSYB3 BUSYB2 BUSYB1 BUSYB0 NCR3 NCR2 NCR1 NCR0 When the ERR bit 0 the NCR and BUSYB signals of each channel are read The NCR signal outputs a L level while this LSI is performing command processing and goes to a H level when the LSI enters a command waiting state The BUSY signal...

Page 52: ...ata of External ROM is 00h It becomes an error when it accesses the External ROM under the condition that the External ROM isn t connected SPMERR SPM pin short error bit This bit is set to 1 if the SPM pin is short to SPP pin or GND SPPERR SPP pin short error bit This bit is set to 1 if the SPP pin is short to SPM pin or GND TSDERR High temperature error bit This bit is set to 1 if the temperature...

Page 53: ... but a prescribed command interval needs taking BUSY NCR STATUS pin status 0 Outputs the NCR signal on the specified channel 1 Outputs the BUSYB signal on the specified channel Channel settings C1 C0 Channel 0 0 Channel 0 initial value 0 1 Channel 1 1 0 Channel 2 1 1 Channel 3 CSB SCK SI NCR BUSYB OUTSTAT command CBUSYB internal internal STATUS output STATUS NCR output BUSYB output CSB SCK SI NCR ...

Page 54: ...re used to set the temperature detection level Tj 140 C or OFF can be selected as the judgment temperature The temperature is monitored each time it reaches the value set by TM2 0 and if the temperature reaches or exceeds the set value two times or more the ERR pin outputs a H level and the RDSTAT command s TSDERR bit is set to 1 If the ERR pin is set to a H level check the error contents using th...

Page 55: ...using the power dissipation Tamax 130 C θja C W PD W The maximum ambient temperature Tamax in power supply voltage 5 0V and θja 36 C W is as follows Tamax 130 C 36 0 861 99 C The TM2 0 bits are used to set the monitor interval to detect a low voltage or temperature TM2 TM1 TM0 Monitor interval 0 0 0 Constantly monitors 0 0 1 2 ms initial value 0 1 0 4 ms 0 1 1 8 ms 1 0 0 16 ms 1 0 1 32 ms 1 1 0 64...

Page 56: ...STAT command BLDERR of the RDSTAT command and the ERR pin keep outputting H even if the ERCL command is inputted Timing diagram for when an error occurs at the time of setting the two time command input mode Timing diagram for when an error occurs at the External ROM ERR tCB1 internal 00h 01h RDSTAT ERR register 00h START command 2nd times ERCL command 1st time ERCL command 2nd times VOH VOL CSB S...

Page 57: ... SAFE command s BLD2 0 bits 001h If a power supply voltage error occurs but the power supply voltage is not returned ERCL command CSB SCK SI VOH VOL CBUSYB tCB1 ERR internal 00h 02h 00h 2 6V 3 0V 3 0V DVDD RDSTAT ERR register ERCL command CSB SCK SI VOH VOL CBUSYB tCB1 ERR internal 00h 02h 2 6V 3 0V DVDD RDSTAT ERR register ...

Page 58: ...own ERCL 2 SPM pin short error Serial I F ERR Speaker short State AMODE spkr_powerup ERCL AMODE spkr_powerdown RDSTAT 00h 10h 2 00h RDSTAT ERR reg internal AMODE spkr_powerup Serial I F ERR Speaker short State AMODE spkr_powerup ERCL AMODE spkr_powerdown RDSTAT 00h 10h 2 00h RDSTAT ERR reg internal AMODE spkr_powerup 10h Serial I F ERR Speaker short State AMODE spkr_powerup ERCL 00h 10h 2 RDSTAT E...

Page 59: ... and ERCL commands 2 Byte Command Input Flow applied to the AMODE AVOL FAD FADR PLAY MUON CVOL and SAFE commands Status Read Flow Input command End CBUSYB H Y N Start CBUSYB H N Y Input the 1st byte of command CBUSYB H Input the 2nd byte of command End CBUSYB H Y N Y N Start CBUSYB H Y N RDSTAT command CBUSYB H Read status SI L Y N ...

Page 60: ...Start Flow Example of Playback Stop Flow Apply power Drive RESETB L Waited for 10 µs Drive RESETB H Y N PUP command AMODE command Power down state Playing STOP command Power up state PLAY command FADR command START command Single channel playback Multi channel playback N Idle not playback Y ...

Page 61: ...r Down Flow Looping CLOOP command STOP command Stop after playback is finished all the way through the phrase Stop playback forcibly Power up state PDWN command PLAY START MUON command Playback playing PLAY START MUON command Within 10mS PLAY START command Playback playing SLOOP command Within 10mS ...

Page 62: ...P command 1st byte of AMODE command CBUSYB H 2nd byte of AMODE command CBUSYB H CBUSYB H Y N Y N Y N Y N CBUSYB H 2nd byte of PLAY command Y N A A BUSYB H RDSTAT command PDWN command Power down state CBUSYB H CBUSYB H Y N Y N Y N CBUSYB H Read status Y N 1st byte of AMODE command CBUSYB H 2nd byte of AMODE command CBUSYB H Y N Y N ...

Page 63: ...RDSTAT command Read status Playback end Y N Y N 1st byte of AMODE command 2nd byte of AMODE command CBUSYB H Y N waiting for command CBUSYB H Y N ERR H It is confirmed that SPMERR or SPPERR is H Speaker Mode is set Power Down ERCL command CBUSYB H Y N Err bit and Err port are cleared STOP command ...

Page 64: ... the PDWN STOP SLOOP CLOOP RDSTAT OUTSTAT and ERCL commands N One time command input End Two time command input CBUSYB H ERR L One time command input Re input End CBUSYB H ERR L One time ERCL command input Y Y Y Y N N N N Two time ERCL command input Y N ERR L CBUSYB H Two time command input Re input ...

Page 65: ...End Two time command input 1Byte One time command input 1Byte Re input Two time command input 1Byte Re input One time ERCL command input Y Y Y Y N N N N Two time ERCL command input Y N One time command input 2Byte Two time command input 2Byte Y N Y N One time ERCLcommand input Y N Two time ERCLcommand input Y N CBUSYB H ERR L CBUSYB H ERR L ERR L CBUSYB H ERR L CBUSYB H ERR L CBUSYB H ...

Page 66: ...F 20 The larger the connection capacitance the longer the speaker amplifier output pin SPM and SPP voltage stabilization time Handling of the VDDL Pins The VDDL pin is the power supply pins for the internal circuits Connect a capacitor between each of these pins and the ground in order to prevent noise generation and power fluctuation The recommended capacitance value is shown below however it is ...

Page 67: ...lifier power supply SPVDD and Speaker amplifier ground SPGND External ROM interface power supply IO VDD As shown in the figure below be sure to diverge the wiring of DVDD and SPVDD from the root of the same power supply DGND SPGND is similar too IOVDD is sure to wire External ROM power supply DVDD SPVDD DGND SPGND 5V IOVDD 3 3V 1 1 IOVDD is sure to wire External ROM power supply ...

Page 68: ...z 15pF 15pF speaker IOVDD VDDL DVDD SPVDD DGND SPGND 0 1µF 0 1µF 1IOVDD is sure to wire External ROM power supply External ROM 5V 0 1uF 0 1uF 10uF 10uF 10uF 3 3V 1 0 1uF speaker 0 1µF SP AMP SPM SPP SG AIN RESETB CSB SCK SI SO CBUSYB ERR STATUS DIPH TESTI1 FLW ECSB ESCK ESO ESI XT XTB MCU 4 096MHz 15pF 15pF IOVDD VDDL DVDD SPVDD DGND SPGND 5V 0 1µF 0 1µF 10uF 3 3V 1 1IOVDD is sure to wire External...

Page 69: ...ty C1 pF C2 pF Rf Ohm Rd Ohm Supply voltage Range V Operating Temperature Range C 4 096M PBRV4 096MR50Y000 15 internal 4 5 to 5 5 40 to 125 MURATA Corporation Freq Hz Type Optimal load capacity C1 pF C2 pF Rf Ohm Rd Ohm Supply voltage Range V Operating Temperature Range C 4M CSTCR4M00G55B R0 39 internal 4 5 to 5 5 40 to 125 4 096M CSTCR4M09G55B R0 Circuit diagram C1 C2 GND XT XTB DGND SPGND DVDD S...

Page 70: ...mitation on the operation time changes by the heat designs of the board PACKAGE HEAT RESISTANCE VALUE REFERENCE VALUE The following table is the package heat resistance value θja reference value This value changes the condition of the board size layer number and so on The board θja The condition JEDEC 4layers 1 W L t 76 2 114 5 1 6 mm 24 6 C W No wind 0m s the soldering area ratio 3 100 JEDEC 2lay...

Page 71: ...nting contact a ROHM sales office for the product name package name pin number package code and desired mounting conditions reflow method temperature and times Notes for heat sink type Package This LSI adopts a heat sink type package to raise a radiation of heat characteristic Be sure to design the land pattern corresponding to the heat sink area of the LSI on a board and solder each other The hea...

Page 72: ...8 Change Application Circuit FEDL22594 06 Oct 16 2017 2 2 Differences table correction 3 Add Playback method 5 6 6 7 Add instructions 8 9 Add instructions to DC Characteristics 12 13 Add instructions to AC Characteristics 13 14 Modify CPU Serial Interface Data Timing 15 15 Modify Power On Timing 15 15 Modify Power Shut down Timing 23 23 Add tINTC 24 Add To know the volume controls more 25 25 Modif...

Page 73: ... to be radiation tolerant 7 For use of our Products in applications requiring a high degree of reliability as exemplified below please contact and consult with a LAPIS Semiconductor representative transportation equipment i e cars ships trains primary communication equipment traffic lights fire crime prevention safety equipment medical systems servers solar cells and power transmission systems 8 D...