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41
DM35418HR/DM35218HR
User’s Manual
BDM-610010041 Rev F
B[7:4]: Status
o
0x08: Uninitialized – The status when in the “Uninitialized” mode and the converter requires initialization.
o
0x09: Initializing
o
0x00: Stopped – The status when in the “Reset” mode, or in the “Uninitialized” mode and the converter does not require
initialization.
o
0x01: Filling Pre-Trigger buffer
o
0x02: Waiting for start trigger
o
0x03: Sampling/Waiting for stop trigger
o
0x04: Filling Post-Stop buffer
o
0x05: Wait to re-arm – Waiting until local FIFO is empty so the pre-trigger buffer can be filled.
o
0x07: Done capturing
6.4.3
CLK_SRC
(R
EAD
/W
RITE
)
Selects the source for CLK_DIV from the clock bus.
Below is the list of clock sources and the register value needed to select the source.
B[7:0]:
o
0x00: System clock/immediate
o
0x01: Never
o
0x02: CLK_GBL2
o
0x03: CLK_GBL3
o
0x04: CLK_GBL4
o
0x05: CLK_GBL5
o
0x06: CLK_GBL6
o
0x07: CLK_GBL7
o
0x08: Channel Threshold – One of the channels has exceeded the High or Low threshold.
o
0x09: Channel Threshold Inverted– All of the channels are within the High and Low threshold.
o
0x0A: CLK_GBL2 Inverted
o
0x0B: CLK_GBL3 Inverted
o
0x0C: CLK_GBL4 Inverted
o
0x0D: CLK_GBL5 Inverted
o
0x0E: CLK_GBL6 Inverted
o
0x0F: CLK_GBL7 Inverted
6.4.4
START_TRIG
(R
EAD
/W
RITE
)
Selects the start trigger from the clock bus. CLK_DIV will start counting after the start trigger, unless PRE_TRIGGER_CAPTURE is non-zero
in which case CLK_DIV will start counting immediately.
section above, for list of valid values.
6.4.5
STOP_TRIG
(R
EAD
/W
RITE
)
Selects the stop trigger from the clock bus.
section above, or list of valid values..
6.4.6
CLK_DIV
(R
EAD
/W
RITE
)
Divider for the pacer clock. Pacer Clock Frequency = (Clk_Src_Frequency) / (1 + CLK_DIV). If synchronizing with the pacer clock from
another Function Block (by using one of the CLK_GBL signals), this is typically set to 0.
6.4.7
CLK_DIV_CNTR
(R
EAD
O
NLY
)
The current value of the Clock Divide Counter. This counter starts at a value of CLK_DIV, and counts down. When it reaches zero, a sample is
taken. This is useful when using a slow sample clock.
