UPS25 31
RTD Embedded Technologies, Inc
Interrupt request lines
To allow different peripheral devices to generate interrupts on the same computer,
the PC AT bus has interrupt request channels (IRQs). A rising edge transition on
one of these lines will be latched into the interrupt controller. The interrupt
controller checks to see if the interrupts are to be acknowledged from that IRQ
and, if another interrupt is being processed, it decides if the new request should
supercede the one in progress or if it has to wait until the one in progress has
been completed. The priority level of the interrupt is determined by the number of
the IRQ as follows; IRQ0 has the highest priority whilst IRQ15 has the lowest.
Many of the IRQs are used by the standard system resources, IRQ0 is dedicated
to the internal timer, and IRQ1 is dedicated to the keyboard input, IRQ3 for the
serial port COM2, and IRQ4 for the serial port COM1. Often interrupts 2,5 and 7
are free for the user.
8259 Programmable Interrupt Controller
The chip responsible for handling interrupt requests in a PC is the 8259 Interrupt
Controller. To use interrupts you will need to know how to read and set the 8259's
internal interrupt mask register (IMR) and how to send the end-of-interrupt (EOI)
command to acknowledge the 8259 interrupt controller.
Interrupt Mask Register (IMR)
Each bit in the interrupt mask register (IMR) contains the mask status of the
interrupt line. If a bit is set (equal to 1), then the corresponding IRQ is masked,
and it will not generate an interrupt. If a bit is cleared (equal to 0), then the
corresponding IRQ is not masked, and it can then generate an interrupt. The
interrupt mask register is programmed through port 21h.
End-of-Interrupt (EOI) Command
After an interrupt service routine is complete, the 8259 Interrupt Controller must be
acknowledged by writing the value 20h to port 20h.
