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CHAPTER 6
What happens when an interrupt occurs?
6.1 What happens when an interrupt occurs?
• The CPU-core receives an interrupt request from the interrupt controller.
• As soon as the interrupts are enabled, the interrupt is accepted and executed.
• The CPU pushes temporary registers and the return address onto the current stack.
• The CPU switches to handler mode and main stack.
• The CPU saves an exception return code and current flags onto the main stack.
• The CPU jumps to the vector address delivered by the NVIC.
• The interrupt handler is processed.
• The interrupt handler ends with a return from interrupt by reading the exception return
code.
• The CPU switches back to the mode and stack which was active before the exception
was called.
• The CPU restores the temporary registers and return address from the stack and
continues the interrupted function.
6.2 Defining interrupt handlers in C
Interrupt handlers for Cortex-M cores are written as normal C-functions which do not take
parameters and do not return any value. Interrupt handlers which call an embOS function
need a prologue and an epilogue function as described in the generic manual and in the
examples below.
Example
Simple interrupt routine:
static
void
_Systick(
void
) {
OS_INT_EnterNestable();
// Inform embOS that interrupt code is running
OS_TICK_Handle();
// May be interrupted
OS_INT_LeaveNestable();
// Inform embOS that interrupt handler is left
}
6.3 Interrupt vector table
After reset, ARM Cortex-M CPUs use an initial interrupt vector table located in ROM at
address
0x00
. It contains the initial stack pointer as well as the addresses of all exception
handlers, which are defined in a C source or assembly file in the CPU specific subdirectory.
All interrupt handler function addresses have to be present in that file at compile time as
long as the table is kept in ROM.
If the vector table is copied to RAM, however, interrupt handlers can be installed dynamically
at runtime. To do so, the vector table base register inside the NVIC controller has to be
initialized to point to the vector table base address in RAM.
6.3.1 Required embOS system interrupt handler
embOS for Cortex-M core needs two exception handlers which belong to the system itself,
PendSV_Handler()
and
SysTick_Handler()
. Both are delivered with embOS. When using
your own interrupt vector table, ensure that they are referenced in the vector table.
Note
Some older BSPs used to name the PendSV ISR
OS_Exception()
and thus need to
rename it to
PendSV_Handler()
.
embOS-MPU for Cortex-M and IAR
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