12
SiFive E300 Platform Reference Manual, Version 1.0.1
31
30
19
18
17
16
15
12 11 10
9
4
3
2
0
plllock
0
pllbypass
pllrefsel
pllsel
0
pllq
pllf
0
pllr
1
12
1
1
1
4
2
6
1
3
Table 4.3: The PLL config register,
pllcfg
.
÷R
pllr[1:0]
=1,2,3,4
×
F
pllf[5:0]
=2,4,..,128
÷Q
pllq[1:0]
=2,4,8
pllref
refr
vco
pllout
6-48MHz
6-12MHz
384-768MHz
48-384MHz
Figure 4.2: Controlling the E300 PLL output frequency.
reference divider (
refr
) must lie between 6–12 MHz.
The
pllf[5:0]
field encodes the PLL VCO multiply ratio as a 6-bit binary value,
N
, signifying a
divide ratio of
2
×
(
N
+ 1)
(i.e.,
000000
=2,
111111
=128). The frequency of the VCO output (
vco
)
must lie between 384–768 MHz. Table 4.4 summarizes the valid settings of the multiply ratio.
Legal
vco
pllf
frequency
refr
multiplier
(MHz)
(MHz)
Min
Max
Min
Max
6
64
128
384
768
8
48
96
384
768
10
39
76
390
760
12
32
64
384
768
Table 4.4: Valid PLL multiply ratios. The multiplier setting in the table is given as the actual multiply
ratio; the binary value stored in
pllf
field should be
(
M/
2)
−
1
for a multiply ratio
M
.
The
pllq[1:0]
field encodes the PLL output divide ratio as follow,
01
=2,
10
=4,
11
=8. The value
00
is not supported. The final output of the PLL must have a frequency that lies between 48–384 MHz.
The one-bit read-write
pllbypass
field in the
pllcfg
register turns off the PLL when written with a
1 and then
pllout
is driven directly by the clock indicated by
pllrefsel
. The other PLL registers
can be configured when
pllbypass
is set. The agent that writes
pllcfg
should be running from a
different clock source before disabling the PLL. The PLL is also disabled with
pllbypass
=1 after a
wakeup reset.
The
pllsel
bit must be set to drive the final
hfclk
with the PLL output, bypassed or otherwise.
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