4/17/17
SigMRF Users Guide, Rev A2
Copyright
Signalogic, Inc. 2016-2017
5 / 39
2.2.3 coCPU™ Option
SigMRF supports coCPU hardware options to (i) substantially increase platform transcoding
capacity, (ii) enable transcoding in very small-form factors, and (iii) provide reduced packet
latency if needed for certain applications (using NICs located directly on the coCPU hardware,
as shown in Figure 2-1 below).
As one example, 64 to 256 coCPU cores can be added to a 1U server; as another example, a 14-
slot ATCA rack can host 1920 coCPU cores. These high levels of core density are suitable to
address applications constrained in space and power consumption.
From a software architecture perspective, in the diagram in Figure 1-1 above, which uses a
partial 3D representation, DirectCore forms a “dividing layer” between x86 CPUs in front of the
layer and coCPUs behind the layer. If coCPU hardware is in use, the SigMRF background
process, as well as packet and media libraries, exist on both sides of this layer.
The coCPU Users Guide is located at
ftp://ftp.signalogic.com/documentation/Hardware/SigC667x/SigC667x_UserGuide_RevD2.pdf
.
coCPU Hardware Options
coCPU hardware options include:
•
32-core and 64-core PCIe cards
•
160 core ATCA blades
coCPU hardware uses Texas Instruments CPUs (8-core c66x devices) which provide the
following benefits:
•
State-of-the-art CPU architecture, including multicore, L2 cache, DDR3 external mem,
onchip PCIe and network I/O, onchip wire-speed packet processor including UDP port
filtering, high clock rate SIMD instruction architecture, and extensive onchip DMA
•
Run standard C/C++ software without undue modifications, including open source
packages of various types
•
Build tools generate highly optimized, efficient run-time codes, especially for
calculation-intensive applications such as codecs, analytics, neural net convolutions, etc.
Figures 2-1 through 2-4 below show examples of coCPU hardware installed in various off-the-
shelf server platforms.
