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ATCA-F125 (6873M Artwork) Installation and Use (6806800J94N)
U-Boot
U-Boot
5.8.1
POST Routines
The following table describes that POST routines are performed.
Table 5-5
SYS FW PROGRESS IPMI Sensor - POST Error Event Codes
Event Data (Byte 3)
Description
0x1E
Error accessing the switch devices
0x03
Error in network loop back test
0x20
Error in network PHY test
0x1F
Error in glue logic (FPGA) test
0x0A
Error in I2C bus test
0x16
Error in RTC test
0x09
Error in flash test
0x21
Error in CPU test
0x22
Error in PCI bus test
Table 5-6
POST Routines
Device
Description
CPU
Check PLL configuration (PORPLLSR register).
Check device configuration (PORDEVSR register)
FPGA
Register sanity check. The version code is checked. It must not be 0x00
or 0xFF.
DRAM
Address line and data-line test.
Switch devices
The PCI interface is checked as follows:
Check for configuration space access (vendor/device ID)
Perform walking-one test on first memory-mapped register
Base interface
extender/SPI
Data test on LED register page 0, offset 0x12
I2C buses
Check whether bus addresses 0x50,0x51, 0x52 are accessible on bus
0 and 0x50, 0x6E on bus 1.
RTC
Checks whether the second counter is advancing.
Compares the number of CPU ticks in one second against the expected
system clock frequency (66 MHz)
