Field Programmable Gate Array Registers
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3-19
3
Latch Enable Register
The Latch Enable Register (LEN) resets latches in the Field Programmable
Gate Array (FPGA) for the FAN, TEMP, ALARM_B, ALARM_B and
ENUM alarms. Refer to
. This register is write only. Write a
logic 1 to clear the latch for that bit position. Writing a logic 0 has no effect
on the latch.
SMB_ALERT (Bit 0) - SMB Alert Signal
This bit is set automatically when a SMB_ALERT event is signaled by an
SM bus device.
❏
Write a logic 1 to clear the SMB_ALERT input latch
❏
Writing a logic 0 has no effect
TEMP (Bit 1) - CPU Temperature Signal
This bit is set automatically when a TEMP event is signaled by an off-card
thermostat device.
❏
Write a logic 1 to clear the TEMP input latch
❏
Writing a logic 0 has no effect
ALARM_B (Bit 2) - LM81 Alarm B Signal
This bit is set automatically when an ALARM_B event is signaled by the
on-card LM81.
❏
Write a logic 1 to clear any latched ALARM_B events
❏
Writing a logic 0 has no effect
Table 3-17. Bit descriptions for the LEN register
7 (most
significant
bit)
6
5
4
3
2
1
0
RES
RES
RES
ENUM
ALARM_A
ALARM_B
TEMP
SMB_
ALERT
Solution Systems Technologies Inc.
720-565-5995 | info@solusys.com | www.solusys.com
Solution Systems Technologies Inc.
720-565-5995 | info@solusys.com | www.solusys.com
