PulseBlaster
Specifications
TTL Specifications
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24 individually controlled digital output lines (TTL levels)
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variable pulses/delays for every TTL line
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25 mA output current per TTL line
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output lines can be combined to increase the max. output current
Pulse Parameters
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50 ns shortest pulse/interval for 512 memory-words models at 100 MHz
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90 ns shortest pulse/interval for 32k memory words models at 100 MHz.
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2 years longest pulse/interval
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10 ns pulse/interval resolution (at 100 MHz)
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32k instructions max. memory space (512 instructions for internal memory models)
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external triggering and reset – TTL levels
Pulse Program Control Flow (Common)
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loops, nested 8 levels deep
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20 bit loop counters (max. 1,048,576 repetitions)
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subroutines, nested 8 levels deep
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wait for trigger – 8 clock cycle latency (80ns at 100 MHz), adjustable to 2 years in duration
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5 MHz max. re-triggering frequency\
http://www.spincore.com
5/19/2006
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