Sun Microsystems 2060, Hardware Engineering Manual

Page 1: ...ering Manual for tIle 2060 CPU Board C011fidential and Proprz etalY Material Sun Microsystems Inc 2550 Garcia Avenue Mountain View CA 94043 415 960 1300 211 0 C ik Part No 800 1386 13 Rev 1 of 10 May 1987 CONFIDENTIAL ...

Page 2: ...urphy Jim Ludemann Bruce Smith Kevin Mobley and Niel Hanes without whose explanation and assistance this manual would never have been written Copyright 1987 by Sun Microsystems Inc This publication is protected by Federal Copyright Law with all rights reserved No part of this publication may be reproduced stored in a retrieval system translated transcribed or transmitted in any fonn or by any mean...

Page 3: ... FC3 4 1 7 Memory Management Unit 4 1 8 Device space 4 1 9 Memory Space TYPED space 5 Parity Main Memory 5 Video Memory 5 1 10 I O Devices TYPEI space 5 1 11 V 1E Master TYPE2 and TYPE3 Space 6 1 12 Interrupts 6 On Board Interrupts __ 6 Vl ffi Vectored Interrupts _ _ 7 1 13 CPU Resets and Timeout _ 7 Chapter 2 VME ComplIance _ _ 11 2 1 Options _ 11 2 2 PerfoIlIlance Parameters _ _ 11 iii ...

Page 4: ... Cache Disable J100 23 5 3 CPU Space PALs U106 and U10 24 5 4 U1tJ6 PAL 26 U106 Input Signals 26 U106 Output Signals 27 5 5 UIO PAL 30 UIO Input Signals 31 UIO Output Signals 31 Chapter 6 Power on Circuitry 37 Chapter 7 Response Synchronizer U206 41 Chapter 8 Reset Pal U201 and User Reset Switch U205 45 8 1 U205 User Reset Switch 45 8 2 U201 Reset PAL 46 U201 Input Signals 46 U201 Output Signals 4...

Page 5: ...1 3 J300 69 Chapter 12 Interrupt Circuitry U302 U304 PALs U305 Register 73 12 1 Interrupt Request Cycle 73 12 2 Interrupt Acknowledge Cycle 74 12 3 Priority 77 12 4 Two Level Priority Encoding 77 12 5 U302 Lower Priority Encoder 78 U302 Pinout 79 U302 Input Signals 79 U302 Output Signals 80 12 6 U303 Higher Priority Encoder 84 U303 Pinout 84 U303 Input Signals 84 U303 Output Signals 85 12 7 Second...

Page 6: ...ter 15 Pal U408 107 IS I Pinout ofU408 PAL 107 Chapter 16 Sun 3 Memory Management Unit MMU 111 Chapter 17 Context Register U509 115 17 1 US09Pinout 116 17 2 US09 Input Signals 116 17 3 US09 Output Signals 117 Chapter 18 Segment Map U500 08 121 18 1 Segment Map Read and Write Cycles 122 Segment Map RAM Read Cycle 122 Segment Map RAM Write Cycle 123 Truth Table for the US08 Buffer 123 18 2 Segment M...

Page 7: ... Generator Checkers U807 04 151 23 3 U803 Multiplexer 152 23 4 Parity Control and Parity Check PALs U802 and U812 152 23 5 U812 Parity Check PAL 153 U812 Input Signals 153 U812 Output Signals 153 23 6 U802 Parity Control PAL 156 U802 Input Signals 156 U802 Output Signals 157 Pinout of U802 PAL 159 23 7 Memory ErrorRegister U801 161 23 8 Byte Select Buffer and Address Bit Driver U813 162 23 9 Parit...

Page 8: ...d and Write Cycles 185 MOS Read Cycle 186 MOS Write Cycle 186 24 6 Mouse and Keyboard SCC 186 U405 and U2207 Baud Rate Clock 187 Transmit Data Path 187 Receive Data Path 187 24 7 Serial Ports A and B ttya and nyb 187 Transmit Data Path 188 Receive Data Path 188 24 8 EEPROM aIld EPROM 188 EEPROM 190 EPROM 190 24 9 Time of Day TOD Dock 190 TOD Oscillator Circuit 190 Chapter 25 TTL Bus Accesses 195 2...

Page 9: ...3 U1405 Ethernet Control Write Buffer 223 U1407 Ethernet Control Read Buffer 224 25 7 System Enable Register 224 U1406 System Enable Write Register 224 U1408 System Enable Read Register 225 25 8 U1410 Diagnostics Register 225 25 9 U1409 ID PROM 225 25 10 U1404 P2 to TTL Data Buffer 225 25 11 U2905 and U2906 User DVMA Enable Register 226 25 12 U203 Bus Error Register 226 25 13 U509 Context Register...

Page 10: ...V1501 Output signals 251 V1500 Buffer and U1505 DIP 253 26 7 Ul608 UI603 Video Controller 253 26 8 V17oo 01 Video RAS CAS Latches 254 26 9 Frame Buffer RM1 255 26 10 ECL Circuitry 256 ECL Oock 256 26 11 Horizontal and Vertical Synch State Machines 257 Chapter 27 VMEbus Perfonnance 263 27 1 2060 VtviE Implementation 263 Chapter 28 VME Arbiter and Requester 269 28 1 Tenninology for VME Arbiter and R...

Page 11: ...VtviE Select and Freeze State Diagram 288 Nonna O Cration 288 Deadlock Resolution 289 V1 1E Shon Timeouts 290 V1 1E Long Timeouts 290 29 3 V ME Master Controller PAL U2806 291 Terminology for V1 1E Master Controller 293 VME Master Controller State Machine 293 CPU Retains Control of 1 1Ebus at End of Cycle 294 CPU Relinquishes Control ofVMEbus at End of Cycle 295 CPU Freeze Cycles 295 Address Modif...

Page 12: ...ycle 315 32 2 Optimizations to the DVMA Cycle 316 Back to Back DVMA 316 Ethernet Hold 316 VIvffibus Lock 316 32 3 Refresh as a SJ ecial Case 316 32 4 The DVMA Strobe PAL U2410 317 Input and Output Signals 319 Chapter 33 Sample Cycles 323 33 1 V1vffi Master Cycles 323 CPU Access of Idle V1vffibus 323 CPU Access of a Busy VMEbus 324 CPU Access of V vfEbus Currently Bus Master 325 CPU Rerun During VM...

Page 13: ...U3I02 Outputs 336 U3100 Output Signals 337 U3102 Output Signals 339 Chapter 35 CAS Decode PAL U3104 345 35 1 U3104 Pinout 345 35 2 U3104 Input Signals 346 35 3 U3104 Output Signals 346 Chapter 36 Control Buffers U3105 and U3115 351 Chapter 37 Rowand Column Address Multiplexers U3110 07 355 Chapter 38 Memory RAM Pages 32 and 33 359 38 1 Memory Read 359 38 2 Memory Write 359 38 3 Processor Data Acqu...

Page 14: ...dress Space 24 Table 5 4 CPU Space Cycles 25 Table 5 5 Coprocessor Designation 25 Table 10 1 Data Size Encodings P2_siz I 0 60 Table 10 2 Base Offset Encodings p2_a 01 00 62 Table 10 3 Dynamic Bus Sizing How dsack 1 0 Decode Port Size 63 Table 11 1 Interrupt Register Sigrtal Designations _ 68 Table 12 1 Low Priority Acknowledge Bit Encodings Ip_ack 1 0 _ 77 Table 12 2 High Priority Acknowledge Bit...

Page 15: ...Bit Decode 128 Table 19 4 Byte Selection in the Page Map RAM 128 Table 21 1 MMU Protection Bits Decode of the Inputs 141 Table 21 2 Truth Table for 1vUv1U Protection Bits 141 Table 22 1 U700 Comparator 147 Table 23 1 Parity State Diagram State Values 157 Table 23 2 Parity State Diagram Description of the States 158 Table 23 3 Memory Error Register U801 162 Table 24 1 Map for TYPEI Space 165 Table ...

Page 16: ...to TTL Data Buffer Data Flow 2Lv Table 29 1 U2806 TraIlSfer gic 294 Table 29 2 Address Modifier Bits on the 2060 Board 296 Table 32 1 MC68020 Data Size Output Encodings 320 Table 32 2 MC68020 Function Code Output Encodings 320 Table 38 1 Memory Data Buffers Data Flow 359 xvii ...

Page 17: ...he 32 bit Bus Spacet 61 Figure 10 3 Word Data Alignment Within the 32 bit Bus Spacet 61 Figure 10 4 3 Byte Data Alignment Within the 32 bit Bus Spacet 61 Figure 10 5 Longword Data Alignment Within the 32 bit Bus Spacct 61 Figure 10 6 Dynamic Bus Sizing Transfer Offsets 62 Figure 12 1 Interrupt Request Cycle _ _ 74 Figure 12 2 Interrupt Acknowledge Cycle _ 75 Figure 12 3 Interrupt and Acknowledge C...

Page 18: ...iagram 160 Figure 24 1 MaS Decoders 166 Figure 24 2 U9 Pinout 167 Figure 24 3 U901 MaS Control State Machine Pinout 170 Figure 24 4 MaS Control State Machine 171 Figure 24 5 MaS DTACK PAL Wait State Counter 175 Figure 24 6 U9 4 Pinout 179 Figure 24 7 U902 MaS Write Data Buffer 184 Figure 24 8 U903 MaS Read Data Buffer 185 Figure 25 1 U1400 Pinout 196 Figure 25 2 TTL Bus DTACK SACK State Machine Di...

Page 19: ...56 Figure 28 1 U2704 Pinout 271 Figure 28 2 VME MASTER State Relationship of S4SEL to B_SSEL 275 Figure 29 1 U2701 Pinout 286 Figure 29 2 U2806 Pinout 292 Figure 30 1 U2907 Pinout 300 Figure 30 2 U2904 Pinout 304 Figure 32 1 U2410 Pinout 318 Figure 34 1 U3100 and U3102 Pinouts 335 Figure 35 1 U3104 Pinout 3 45 Figure 37 1 RAS CAS Decode Bit Assignments for 2 and 4 Mbyte Systems 355 xxi ...

Page 20: ...ike WRITE WRITE or WRlTE the three are synonymous is asserted it is equal to its most negative state D Activated means the same as asserted o Logic 1 in positive logic a logic 1 stands for the more positive of the two voltage levels A logic 1 in negative logic stands for the more negative of the two voltage levels D Logic 0 in positive logic a logic 0 stands for the more negative of the two voltag...

Page 21: ... output When referring to a latch it means that data is flowing through the latch o LATCHED means that the data is held in the latch that is the latch is closed o DIP stands for Dualln line Package and refers to the physical geometry of the chip rectangular with pins on the two longer sides o DIP Switch a multi sectioned switch which has DIP geometry o Switch a device for making or breaking an ele...

Page 22: ...ge Sometimes these values will skip Generally the numbers are assigned in columns which go from left to right Pullups are indicated by pu followed by a functional designator such as puv7 which indicates a pullup used in the video section Other pullups are indicated by h followed by a numerical designator such as hO Pulldowns are indicated by an lpd followed by a numerical designator such as pdO In...

Page 23: ...roller 1 6 Control Space Devices FC3 1 7 Memory Management Unit _ 1 8 Device space 1 9 Memory Space TYPED space Parity Main Memory Video Memory 1 10 I O Devices TYPEI space 1 11 V1vffi Master TYPE2 and TYPE3 Space 1 12 Intenupts On Board Intenupts V1vffi Vectored Intenupts 1 13 CPU Resets and Timeout 3 3 3 4 4 4 4 4 5 5 5 5 6 6 6 7 7 S i 1 ta l A fi i0Y iF ...

Page 24: ... bit D6 O FPP coprocessor cycles are tenninated with an immediate bus error All other coprocessor addresses and accesses to an enabled but uninstalled FPP result in a Timeout bus error Interrupt Acknowledge cycles and installed and enabled FPP cycles tenninate nonnally with DSACK or are aborted with a synchronous bus error 1 2 System DVMA 1 3 VME Slave User DVMA The two system DVMA devices are the...

Page 25: ...e read and byte write except for the bus error register which is byte read only The ID PROM Page Map and Segment Map are implemented as an array of bytes This allows word and longword accesses via the 68020 dynamic bus siz ing capability Control Space Devices and Their Addresses ADDRESS DEVICE OxOOOOOOOO Vinual IDPROM Ox100000oo Vinual Page Map Ox20000000 Virtual Segment Map Ox300000oo Context Reg...

Page 26: ...e first is a 1152 by 900 pixel fonnat and the second is a 1024 by 1024 lK by 1K format The Vertical rate will be 67 Hz and the pixel rate ill be 10 nsec per pixel Outputs to the video monitor are as follows 1 Serial Video differential ECL 2 Horizontal Sync positive TIL pulse sync on rising edge 3 Vertical Sync positive TIL pulse sync on rising edge The following devices are implemented in TYPE1 21...

Page 27: ...TVPE3 Space Table 1 3 CPU accesses to the VMEbus will be through TYPE2 space for 16 bit data transfers and TYPE3 space for 32 bit data transfers The 32 bit address will be decoded to supply the VME Address Modifier bits and define the V1 1E address size TYPE2 Space TYPE2 32 bit Address VMEbus with 16 bit data AM5 3 H Address Afodifiers OxOOOOOOOO VME 32 bit address space LLH OxFFOOOOOO VME 24 bit ...

Page 28: ...terrupts VME interrupts are vectored and at lower priority than on board interrupts 1 13 CPU Resets and Timeout 1 Power On Reset see 7 0 2 Watchdog Reset see 7 0 A user accessible panic button RESET will also force a watchdog reset 3 CPU Reset see 7 0 In addition access to the VMEbus will be inhibited for the 200 msec min SYSRESET period 4 CPU Board Timeout Minimum of one refresh period maximum of...

Page 29: ...I _ 2 VME Compliance VME Compliance 11 2 1 Options 11 2 2 PerfoITl1aIlce ParaITleters 11 i ...

Page 30: ...ffi Slave or VME User mode since it is each master s responsibility to provide its 0 11 timeout 5 Backoff Mechanism If the CPU initiates an access to the VME at the sarro time that a VME device accesses the P2 the CPU cycle will back off and be re run 6 Non implemented features Since multiprocessing will not be allowed on our systems READ MODIFY WRITE is not implemented The ACFAll timing during po...

Page 31: ...bus master assume idle P2 bus AS to DTACK 570 630 nsec J 4 VME to P2 bandwidth assume P2 bus locked bandwidth s VME to VME transfer time to acquire VMEbus bandwidth 6 3 8 9 MBytes sec 635 450 nsec longword 70 155 nsec limited by VME spec and VME devices Rev 1 of 10 May 1987 C01 TIDE lIAL ...

Page 32: ...3 Block Diagram Block Diagram 15 3 1 Data Patl1s 16 ...

Page 33: ...cessed in FC3 space The MMU translates the vinual address into a physical address Device Space that is used by the devices accessed through the MMU This Device Space is divided into four types o typeD for main and video memory o type1 for I O and Control devices and o type2 3 for the VME Master interface 2060 Block Diagram MMU CPU 68020 68881 FPA Ethernet Interface VME Slave Interface Control Spac...

Page 34: ...face bandwidth will be lower than maximum because of the 8 bit bus restriction but accesses to these devices will be infrequent and the loss of bandwidth not noticeable The dynamic bus sizing capability of the 68020 is used so that longword moves can be made to these two devices To segregate the MOS devices from the devices two separate 8 bit buses are used The two types of devices have different ...

Page 35: ...4 Mechanical Specifications Mechanical Specifications 19 4 1 Board FOI111 Factor 19 4 2 Connectors 19 4 3 Switches 19 ...

Page 36: ...U board 1 PI P2 and P3 96 pin VMEbus connectors 2 9 pin video output 3 15 pin Ethernet 4 two 25 pin serial ports and 5 I5 pin long distance keyboard and mouse connector The basic Expansion board has the three YMEbus connectors PI P2 and P3 Additional connectors depend on what other functions besides memory are on the board There are two user accessible switches One is the diagnostic switch which i...

Page 37: ... Point Coprocessor and Associated Circu it 23 5 1 Processor Data Buffers UI05 2 23 UI05 2 Data Flow 23 5 2 Cache Disable 1100 23 5 3 CPU Space PALs UI06 and UI07 24 5 4 U1C 6 PAL 26 lJ 106 Input Signals 26 UI06 Output Signals 27 5 5 UI07 PAL 30 U107 Input Signals 31 U107 Output Signals 31 ...

Page 38: ... performing a cycle or 2 a DMA cycle is being performed This enabling disabling action is controlled by the p_bufen signal from UI0 CPU space PAL UlOS 2 Data Flow Direction of the data flow is controlled by the processor read write signal p_rn when p_rw is high a read data flows from the P2 data bus to the processor when it is low write data flows from the processor to the P2 data bus The truth ta...

Page 39: ...gram 0 1 1 Control Space 1 0 0 Reserved 1 0 1 Device Space Supervisor Data 1 1 0 Device Space Supervisor Program 1 1 1 CPU Space Looking at this table you will notice that address space is divided into three kinds of space 1 Device Space Function Codes L 2 5 and 6 2 Control Space Function Code 3 3 CPU Space Function Code 7 NOTE Attempted access to address spaceforfunction codes 0 and 4 is illegal ...

Page 40: ... address bits have meaning in that they are decoded only the lower 28 address bits are translatable through the MMU Thus vinual address space is defined as sixteen contiguous 256 Mbyte 28 bit virtual address spaces These sixteen address spaces are decoded by the four high order address bits not translated through the MMU A 31 28 User space is defined as either A31 28 OxO 0xE in the case where you ...

Page 41: ...el 2 19 Ip2_fpa p fcO 3 lS Ifpp_cs p a3l 17 I pa_bei p a30 5 16 Iclkinh p a29 6 15 Ib c p a28 7 14 Idevspc len boc 8 2 Ic lspc It Is c 7 a 9 2 fpa De gnc lC 11 fpaer Inputs to the UI06 PAL are p_fc 2 0 unbuffered processor function codes p_a 31 28 unbuffered processor virtual address bits en boot s dma fpaen special boot state must go to EPROM cycle is a DVMA cycle timing must be same as p_fc 2 0 ...

Page 42: ...lock generator used for clock stretch through PAL U400 The PAL equation for the bootcy signal is bootcy Is_drna en_boot p_fc2 p_fcl p_fcO p_a31 p_a30 p_a29 p_a28 s_dma en_boot p_fc2 p_fcl p_fcO p_a3l p_a30 p_a29 This equation indicates that the bootcy signal will be active Oow when o you are not in a DMA cycle o you are in boot state o you are in FC6 which indicates a superviser program access in ...

Page 43: ...28 OxO or OxF while you are in boot state The PAL equation for the ctlspc signal is C_t_l_S_ P _C__ 8 _1S dma __ _I_P__f_c_2_ _P_ _f_ c _l_ _P_ _f_c_o l This equation says you may do a valid control space access when CJ you are not in a DMA cycle and CJ the function code equals FC3 The PAL equation for the p2_fpa signal is p2_fpa Is_dma fpaen Ip_fc2 p_fcl Ip_fcO p_A31 p_A30 p_A29 p_a28 Is_dma fpae...

Page 44: ..._feO p_a31 p_a30 p_a29 p_a28 s_dma fpaen len_boot p_fel p_fcO p_a3l p_a30 p_a29 p_a28 This equation says you generate a bus error when you attempt to access the FPA when the FPA is not enabled fpaen is false The PAL equation for the clock inhibit signal clkinh is clkinh s_dma fpaen p_fc2 p_fcl p_fcO p_A31 p_a30 p_a29 p_a28 s_dma fpaen p_fcl p_fcO p_a3l p_a30 p_a29 p_A28 s_dma fpaen len_boot p fel ...

Page 45: ...second half of the CPU Space decoder PALs is U107 It decodes function code bits FC2 0 address bits AI7 I3 a pair ofrenm signals address strobe and the FFP enable signal to generate 5 CPU space control signals Pinout of the UI07 PAL is UJ07 Pinout s dma 1 P a 1 p feL 2 p fc 3 F fcC p a17 5 F_alE E p a15 7 1l p aH 8 p_a13 9 1l g 1C 10 20 vcc 19 p bufe 18 p_as 17 p2reru 16 brerur 5 Ire l p_ir a 13 fp...

Page 46: ...n request from FPA board via p2 bus VI07 Output Signals Outputs from the UID PAL are rerun interrupt acknowledge cycle quick berr when FPP is not enabled output enable for bidirectional P2 68020 data buffers chip select for 68881 logical OR of b_rerun and sp2_rerun Remember that CPU space is divided into either o a coprocessor access or o an interrupt acknowledge cycle as decoded by address bits A...

Page 47: ...nta is A bus error signal is generated immediately if a 68881 cycle is attempted without first enabling the FPP The PAL equation for the bus error signal fpp_berr is fpp_berr CPUSPACE COPROCESSOR FPP_ID en_fpp The signal p_bufen is the output enable gating signal for the P2 data buffers U105 2 The signal is activated every cycle p_as is valid unless the FPP is selected or unless it is a DVMA cycle...

Page 48: ... It is valid as long as you are doing a CPU space access function code equals Fe7 you are addressing a coprocessor A17 16 equal binary 10 address bits A15 13 decode to the FPP equal a binary 01 the FPP is enabled and you are not in a DV 1A cycle We OR the two sources of rerun DVMA and FPA here inside this PAL simply because the necessary pins were available _r_e_ru_n__ _b_r_e_r_u_n_ _ p _2_r_e_r_u...

Page 49: ... _ 6 Power on Circuitry Po er on Circuitr 37 ...

Page 50: ...rator by comparing the voltage from the charge capacitor with the reference voltage This comparator asserts its output until the voltage across the charge capacitor corresponds to a vee of 4 5 volts The bottom comparator forms a power off reset generator by comparing the 5 T supply with the reference This comparator asserts its output when the SV sup ply voltage is below 4 5 volt without the charg...

Page 51: ...7 Response Synchronizer U206 Response Synchronizer U206 41 ...

Page 52: ...2_rerun are activated during cs2 when cs2 signal to the presets is a high and the D input to the flip flops is active Oow Note that sp2_berr is a high active signal for software use so it is taken off the Q output of the flip flop The sp2_rerun signal being low active is taken off the non inverting output Q of U206 Both p2_berr and p2_renm are used exclusively by the FPA board 41 Rev 1 of 10 May 1...

Page 53: ...8 Reset Pal U201 and User Reset Switch U205 Reset Pal U201 and User Reset Switch U205 45 8 1 U205 User Reset Switch 45 8 2 U201 Reset PAL 46 U201 Input Signals 46 U201 Output Signals 47 i h ...

Page 54: ...AG NORM switch and the video connector Pressing this switch forces a watchdog reset which drops you down into the monitor program Sun 3 Connectors on the 2060 CPU Board IETHERNET I LEDO LEOs LED 0 diag position DIAG DIAGNOSTICS 0 NORM boot position RESET VIDEO 1 KEYBOARD MOUSE ISERIAL I PORTA ISERIAL I PORTB 45 Rev 1 of 10 May 1987 CO FIDE TlAL ...

Page 55: ...r it fpo 9 2 fb rs o _ It g lC 3 8 foe Inputs to the U201 PAL are listed below The following signals are used for watchdog resets drops you into the monitor PROM button Processor halt either rerun or double bus error Doing cycle rerun else p_halt triggers watchdog signal Indicates user reset switch has been pushed which is the same as a watchdog reset A very slow clock signal cslow is used to gene...

Page 56: ...re connected to the same bidirectional pin They are mapped together in a post processing stage Outputs from the U201 PAL are init board level initialize signal watchdog watchdog reset occurred drops you into the monitor used as a status bit in the bus error register b_rstout VMEbus reset p_reset processor reset These signals are derived from a complex series of state equations which you can find i...

Page 57: ...9 U202 and U203 Bus Error PAL and Register U202 and U203 Bus Error PAL and Register 51 9 1 U202 Inputs 51 9 2 Pinout of U202 PAL 52 9 3 U202 Output Signals 53 9 4 U203 Bus Error Register 56 ii i i i ...

Page 58: ...othing responded to this cycle bus error from the VMEbus quick berr when access to the FPP is attempted but FPP has not been enabled spurious interrupt bus error If an interrupt is asserted and then deasserted before an interrupt acknowledge can be run this is known as a purious interrupt The system traps on a spurious interrupt which can occur on any level except Level 3 the Ethernet chip Intel E...

Page 59: ...s processor address strobe acts as a qualifier indicates the cycle is a DMA cycle bus error on P2 bus from FPA bus error as result of attemped access to disabled FPA 9 2 Pinout of U202 PAL Figure 9 1 Pinout of the U202 PAL is U202 Pinout 7 IcE 0 p a 1 _ mm verr 2 t rr n J_perr 3 tout 4 b berr Ifpp_oerr E leint berr 7 Irerun 8 Ip2_as 9 gnd 10 2C vee 190 Is d a 180 sp2 berr 17 Iberr _ 16 Ip_berr 15 ...

Page 60: ...he signal s_halt is a synchronized version of p_halt p_halt is the open collector versiC r Since p_halt is bidirectional R209 pullup resistor is connected to this pm to place the line in a tri state when the sig nal is deasserted The PAL equation for the p_halt signal is if s_halt shalt p_halt s_halt p2_as s_dma rerun The p_berr signal indicates a processor bus error It is asserted when one of the...

Page 61: ... otected pagE The lberr signal latches cenain of the bus error signals into the bus error latch U203 Since there were not enough OR tenns for p_berr bus errors had to be partitioned into 2 groups those that have to be latched into the bus error regis ter and those that don t This is the term used to latch those errors Errors that are not latched into the bus error register are o FPP errors o spuri...

Page 62: ...ot being run cycle is invalid permissions incorrect t out VMEbllS error presyncd error from the FPA FPA is disabled Bus errors that go to the 68020 are latched and bus errors that are caused by V ME cycles excluded vmeberr p2_as 5 dma mmu_verr cycle is invalid p2_as 5 dma mmuyerr permissions incorrect p2_as 5 dma tout timeout p2_as vmeberr hold till end ofcycle Rev 1 of 10 May 19B CO r1DE TIAL ...

Page 63: ...us errors vector automatically to their individual traps so they do not need to be read by software through the bus error register The output enable for the bus error register is supplied by the assertion of rd_berr a low active signal supplied by Ul403 PAL Data is loaded and latched into the register by the upward transition of lberr supplied by U202 bus error PAL NOTE The bus error register latc...

Page 64: ...10 U204 DSACK PAL U204 DSACK PAL 59 10 1 Pinout ofU204 PAL 59 10 2 U204 Input Signals 60 Bus Transfer Size 60 Offset Bits 60 10 3 U204 Outputs 62 ...

Page 65: ... two dsack output lines The dsack output lines are used to infonn the 68020 of the I O data port size Pinout of the U204 PAL is U204 Pinout IIl Ill Ip2_as 1 p a 1 2 vee p2 size 2 9 Icsa p2_siz i 3 18 IvsaeK _ It p2_aO 4 17 Iveopyc p2_al 5 16 IfpF_es ltypO 6 15 Ib do a ck Itsaek 7 1 nu Imsaek 8 13 n1 3 Idcpsaek 9 12 Idsackl gnd 10 11 Ip2_aek 59 Rev 1 of 10 May 1987 CO FIDE TlAL ...

Page 66: ... Offset Bits Table 10 1 The P2 size bits p2_siz 1 0 detennine the size of the data transfer which is to be made by the processor over the data bus This data size is decoded in the following table Data Size Encodings p2_siz 1 0 P2 Size Bits Size of p2 siz 1 p2 siz O Transfer 0 0 longword 32 bits 0 1 byte 8 bits 1 0 word 16 bits 1 1 3 byte 24 bits The two low order P2 address bits p2_a OI 00 are use...

Page 67: ...re 10 3 Figure 10 4 ord Data Alignment Within the 32 bit Bus Spacet 1 3_1 2 4t f j_15 08 I _07 00 1 3 Byte Data Alignment Within the 32 bit Bus Spacet Figure 10 5 Longword Data Alignment Within the 32 bit Bus Spacet je _3_1 2 J4 t j_I_5 0 81I P 7 00 1 Remember that in a write cycle the 68020 drives all 32 lines of the data bus regardless ofthe actual size ofthe transfer This means that all 32 line...

Page 68: ... that a byte transfer may have within a 32 bit longword Figure 10 6 Dynamic Bus Sizing Transfer Offsets 31 24 23 16 15 08 07 00 byte transfer byte transfer byte transfer byte transfer O byte offset i byte offset 2 byte offut 3 bytt offset And so on The table below decodes the different offsets Table 10 2 Base Offset Encodings p2_a Ol 00 P2 Address Bits Size of p2 alOlJ p2 alOO Offset 0 0 obytes 0 ...

Page 69: ...rrent cycle Since every device has a unique address there should never be an occasion when more than one acknowledge is returned at the same time However should more than one acknowledge be returned simultaneously the DSACK PAL will output a no acknowledgen dsack 1 OJ are equal to ones and wait states are insened into the current cycle until a timeout bus error is incurred Rev 1 of 10 May 1987 CO ...

Page 70: ...11 Interrupt Circuitry U301 U300 J300 Interrupt Circuitry U301 U300 J300 67 11 1 InteIllJpt Priority 67 11 2 U301 0 InteIllJpt Enable Registers 68 11 3 J300 69 ...

Page 71: ......

Page 72: ...nterrupt levels one through six are maskable interrupts they are vali dated after comparison with three interrupt status bits in the MC68020 status register 1 If the value in the status register is greater its interrupt priority is higher than this latest interrupt request the latest interrupt request is ignored 2 Ifthe value in the status register is less than or equal to its interrupt priority i...

Page 73: ...rame buffers o EN INT5 enables clock interrupt requests on level 5 When enabled a level 5 interrupt request is set on the rising edge of the clock interrupt out put The level 5 interrupt request is cleared by momentarily turning off the EN INT5 bit D EN INT6 is a reserved bit It can be read from and written to but has no effect o EN INT7 enables clock interrupt requests on level 7 When enabled a l...

Page 74: ...ls of interrupt enable and an eighth signal vinten vertical interrupt enable which clears the vertical interrupt flipflop U2209 in the video section of the board J300 jumper allows you to individually enable or disable interrupts coming from the VMEbus This is a convenience in situations where you are using more than one CPU by allowing you to assign individual interrupts to separate CPUs Rev 1 of...

Page 75: ... 5 U302 Lower Priority Encoder 78 U302 Pinout 79 U302 Input Signals 79 U302 Output Signals 80 12 0 U303 Higher Priority Encoder 84 U303 Pinout 84 U303 Input Signals 84 U303 Output Signals 85 12 7 Second Level Interrupt Priority Encoder U304 89 Pinout of U304 PAL 89 U304 Input Signals 90 U304 Output Signals 90 Sample Interrupt Cycle 92 Spurious Interrupt 92 Ethernet Controller and Spurious Interrup...

Page 76: ...ut no dsack 1 0 bits or autovector signal p_avec is returned to conclude the interrupt acknowledge cycle There are two pans to an interrupt cycle 1 a request CYCle and 2 an interrupt cycle 12 1 Interrupt Request Cycle On interrupt request cycles a device or interrupt request is assened to the either the high or low priority encoder U302 or U303 The interrupt request level is then output from the a...

Page 77: ...alf of an interrupt cycle the interrupt ack nowledge cycle by issuing the acknowledged priority level on three processor address lines p_a 03 01 which are connected to the upper and lower priority encoders U302 and U303 The appropriate encoder issues a 2 bit acknowledge signal to U304 on either o hp_ack l 0 high priority encoder or o lp_ack l 0 low priority encoder U304 then decodes this 2 bit ack...

Page 78: ...owledge cycle is allowed to complete before this new one is initiated D Ifno higher level interrupt is pending or the interrupt pending is of an equal or lower priority than the earlier interrupt about to be serviced the earlier interrupt cycle is completed Thus the progression through an interrupt cycle is Request Pending Acknowledge Service These acknowledge signals encode various types of inter...

Page 79: ... illurrupt is 1101 recognized 2 ReadJWrile sipal asserted 3 FWlCtion Code set to Ox7 CPU space 4 Ill1errupt level placed on p2_a 2 0 addnss lines 5 Size bits siz 1 0J set to trallSjer size 6 Address strobe p2_as tvtd data strolu p2_tis asserted Interrupting Device Providu Vector Number 1 Vector Ilumber generated 2 Port size dsacJc l 0 bits assertedfrom device or 3 Awoveetor gellualed awc asserted ...

Page 80: ...r ity code to the second level encoder U304 over the ipc 2 0 lines The two first level encoders U302 and U303 are daisy chained together by the output enable signal hp_eo which arbitrates between U302 and U303 If U303 deassens the low active hp_eo signal it 1 notifies U304 that U303 will have control of the ipc 2 0 lines and 2 disables U302 the lower level priority encoder This lock out ensures th...

Page 81: ...ous interrupt r 0 0 0 I vmevec low priority section 0 0 1 0 sccvec low priority section ILLEGAL 0 0 I 1 autovec low priority section 0 I X tt X vmevec high priority section I 1 0 X X sccvec high priority section 1 I X X autovec high priority section 12 5 U302 Lower Priority Encoder U302 encodes interrupt levels 4 3 2 1 and 0 the lower level interrupts It also encodes the lower priority acknowledge...

Page 82: ...ec 15 ipc 1 ipc y ipc2 J _ 12 lp_ackl 1 p2_a2 _ U302 Input Signals Inputs to the U302 PAL are software interrupt enables from TTL data bus interrupt requests from the VMEbus Ethernet chip interrupt request p2_a 03 01 P2 address bits which are used by the processor to indicate which level of interrupt is being acknowledged high level priority encoder enable output which is used to disable U302 to a...

Page 83: ...de signals lp_ackl and lp_ackO are the result of the follow ing equations lp_ackl p2_a3 e_irq en_int3 b_irq3 p2_a2 p2_al en_int2 p2_al en_intl p2_a2 p2_a2 p2_al lp_ackO p2_a3 p2_a2 p2_a3 p2_al b_irq4 p2_a2 p2_al en_int2 b_irq2 p2_a2 p2_al en_intl b_irql p2_a2 p2_al p2_a3 Ip2_a2 p2_al The table below contains the PAL logic from which each output signal is derived Rev 1 of 10 May 1987 COr rFIDET lIA...

Page 84: ...autovector Ethernet X 0 I X X X X X 0 I I I 1 level 3 autovector system enable interrupt X 0 0 0 X X X X 0 1 1 0 1 vectored VME interrupt level 3 special case X 0 0 1 X X X X 0 I 1 I 1 spurious EthemeL interrupts X X X X 1 X X X 0 I 0 1 1 level 2 autovector to system enable interrupt X X X X 0 0 X X 0 1 0 0 1 level 2 VME vec tored interrupt X X X X 0 1 X X 0 I 0 0 0 spurious level 2 interrupt X X ...

Page 85: ... int3 hp_eo b_irq3 ipcl hp_eo b_irq4 hp_eo e_irq hp_eo en_int3 b_irq3 en int2 hp_eo en_int3 b_irq3 b_irq2 ipcO hp_eo b_irq4 hp_eo e_irq en int3 hp_eo e_irq b_irq3 en int2 hp_eo e_irq b_irq3 b_irq2 en intl Ip_eo z hp_ eo cannot be asserted when hp_eo is deasserted b_irq4 e_irq en_fnt3 b_irq3 en_int2 b_irq2 en_intl b_irql A _ sun Rev 1 of 10 May 1987 CO FIDEl lIAL Y rTllCfOIystems ...

Page 86: ...0 I I I 1 0 no interrupts 0 0 X X X X X X X 0 0 0 I VME vector level I 4 VME level 4 i 0 I I X X X X X X 0 0 I I Autovector level 3 i ethemet I 0 1 0 1 X X X X X 0 1 0 1 Autovector level 3 I system enable int 0 1 0 0 0 X X X X 0 1 I 1 VfvfE vector level 3 VfvfE leve1 3 0 1 0 0 1 1 X X X 1 0 0 1 Autovector level 2 system enable int 0 1 0 0 1 0 0 X X 1 0 1 1 VfvfE vector level 2 V v1E leve1 2 0 1 0 ...

Page 87: ...0 w p a 1 20 vee 19 hp_aek8 18 p2_a3 17 nu17 16 Ihp_ec _ 15 lipeO 14 lipel 13 lipe2 Jt 2 hp_ack 11 p2 a2 C303 Input Signals Inputs to the U303 PAL are b_irq 7 5 interrupt request from the VMEbus vertint parity circuitry interrupt request time of day clock interrupt on level 7 serial controller interrupt time oi day clock interrupt on level 5 interrupt from the vertical state machine in the video s...

Page 88: ...code signals hp_ackl and hp_ackO are the result of the fol lowing equations hp_8ckl par_irq clk_irq7 p2_82 p2_81 scc_int p2_82 p2_al clk_irq5 p2_a2 p2_81 vertint p2_a2 p2_81 p2_83 hp_ackO par_irq clk_irq7 b_irq7 p2_a2 p2_al scc_int p2_a2 p2_al b_irq6 p2_a2 p2_al clk_irq5 b_irq5 p2_a2 p2_al vertint p2_a2 p2_al p2_a3 The table below contains the PAL logic from which each output signal is derived Rev...

Page 89: ...s level I 7 X I X X a X X X X 1 1 a 1 0 sccvec level 6 I serial chips X X X 1 0 X X X 1 1 0 0 1 VME vector level 6 ME level 6 X I X X 1 1 X X X 1 1 0 a 0 spurious level 6 I I I X I X X X X 1 X X 1 0 1 1 1 Autovector I I I level 5 system I I clock X X X X X 0 0 X 1 0 1 0 1 VME vector level 5 VME level 5 X X X X X 0 1 X 1 0 1 0 0 spurious level I 5 r X X X X X X 1 1 0 0 1 1 Autovector level 4 video ...

Page 90: ...ar_irq clk_irq7 b_irq7 scc int if hp_eo ipcl par_irq clk_irq7 b_irq7 scc_int b_irq6 b_irq7 scc_int clk_irq5 if hp_eo ipcO par_irq clk_irq7 b_irq7 clk_irq7 scc_int b_irq6 clk_irq7 scc_int clk_irq5 b_irq5 hp_eo par_irq clk_irq7 b_irq7 scc_int b_irq6 clk_irq5 b_irq5 vertint The table below contains the PAL logic from which each output signal is derived Rev 1 of 10 May 1987 COSFIDEl j AL ...

Page 91: ... I i 0 I 1 1 1 0 0 X I I 0 1 VME vector level 5 L l _V_ME __ Ie_v_e_1 _5_ _ I 0 0 1 1 1 0 1 1 1 1 1 1 I Autovector level 4 video interrupt I_Of 0 1 1 1 0 1 0 1 1 1 0 no interrupts 1 X X X X X X X 0 0 0 1 Autovector level 7 I m 0 1 X X X X X X 0 0 1 1 Autovector level 7 i system clock I 0 l O X X X X X 0 1 0 1 VME vector level 7 I I VME level 7 I r O l O X X X X O l l l SC C v ec le v e l 6 1 I I s...

Page 92: ... two first level priority encoder PALs U302 and U303 and encodes them to issue as interrupt priority and acknowledge signals Pinout of the U304 PAL is U304 Pinout 1O 1O 1O en int 1 P a 1 20 vee IIp_eo 2 19 b inta ipcO 3 18 Ip_ir c 1O lipe 4 7 p_iplC 1O ipe2 5 16 IF_ lp_ackO 6 15 p_ip12 lp_aekl 7 l 1O li be hp_ec 8 13 Ip_avec hp_ael J 9 12 see aek 1Ir gnd 10 11 hp_aek Rev 1 ofl0May 1987 C01 F1DE TI...

Page 93: ...e being asserted from higher level priority encoder Ip_ack 1 0 encode of vector type being asserted from lower level priority encoder U304 Output Signals Output signals for the U304 PAL are p_ipl 2 0 interrupt priority level sent back to the processor to notify what level interrupt is being asserted int berr b inta scc ack bus error interrupt VMEbus interrupt acknowledge see interrupt acknowledge ...

Page 94: ...als Inputs Outputs Comments en_int hp_eo Ip_eo ipc2 ipcl ipcO p_ip12 p_ipll p_iplo 0 X X X X X 1 1 1 interrupts disabled 1 0 0 X X X 1 1 1 no interrupts active 1 1 X 0 0 0 0 0 0 autovec level 7 parity error 1 1 X 0 0 1 0 0 0 autovec level 7 system clock 1 1 X 0 1 0 0 0 0 vmevec level 7 VME level 7 1 1 X 0 1 1 0 0 1 sccvec level 6 serial chips 1 1 X 1 0 0 0 0 1 vmevec level 6 VME level 6 1 1 X 1 0 ...

Page 95: ...ce interrupt If ver tint is false then the system initiates an interrupt bus error and vectors to the spurious interrupt trap Ifvertint is valid high the interrupt is ack nowledged on the two higher level encoder acknowledge lines hp_ack l 0 D The processor interrupt acknowledge signal p_inta is input to U304 D U304 makes certain that the processor interrupt acknowledge p_inta from U107 is true be...

Page 96: ...r has a feature built into it which allows it to raise and lower its interrupt asynchronously Thus the processor may see an interrupt raised but by the time it has gone out to acknowledge that interrupt it may find that the interrupt request has temporarily disappeared Vhen this happens on interrupt level 3 the system does not vector to the spurious interrupt trap as it would on any other level in...

Page 97: ...on delay on the latch s outputs Any change of data at the inputs will appear within the bounds of this same propagation delay at the latch s outputs e When cs3 is low data is also latched into the latch However data output is not enabled until the assertion of a low active output enable signal Since the outputs are pennanently enabled by the connection of pin 1 output enable to a pulldo 1t TI resi...

Page 98: ...13 ATE Pulldowns U407 ATE Pulldowns U407 97 ...

Page 99: ...tive pulldown resis tors through U407 octal line drivers These line drivers are inverters with out puts permanently enabled by having low active output enables at pins 1 and 19 tied to ground Active pulldo I1s allow ATE overrides for test fixtures 97 Rev 1 of 10 May 1987 C01 TIDE TlAL ...

Page 100: ...14 Clock Generation U40o U406 Clock Generation U400 U406 101 14 1 Pinout ofU400 Clock PAL 101 14 2 U400 Input Signals 102 14 3 U400 Output Signals 103 14 4 U401 Flip Hops 1Q 4 14 5 U402 Flip Flops 1Q 4 ...

Page 101: ...clock may be supplied independently to both the 68020 processor and the 68881 coprocessor by way of the 1400 jumper U400 and U406 Pinout of U400 clock PAL is U400 Pinout 1ft 1ft 1ft es2 3 11ft P a 1 20 vee e60 2 19 oe60 1t e60inv 3 18 oe60inv e60k 4 17 oe60k les4 5 16 loes4 les4 5 6 15 loes4 5 lesS 7 14 loesS les6 8 13 loes6 les 9 12 loes gnd 10 11 lelkinh 101 Rev 1 of 10 May 1987 COl 4FIDEJ IIAL ...

Page 102: ...inverted c60 clock J a constant version of c60 clock labelled c60k This c60k signal is unlike c60 and c60 These last two can be stretched making c4 5 etc The state diagram below illustrates the generation of c60 c60 and c60k The stretch occurs in the transition from state 100 to 101 or 101 to 100 Figure 14 2 Clock Stretch cs4 cs4 5 State Diagram states at each node are c60 c60 and c60k else cs4 s4...

Page 103: ...s4 cs4 5 cs5 cs6 and cs7 The PAL logic from which these output signals are derived is given below TIlj is the code which goes with the clock stretch state diagram given above oe60 oe60inv oe60k e60 e60inv es 5 60 nsec system clock e60 e60inv es4 e 60 inverted 60 nsec system clock es4_5 es4 e60inv le60 Ie e60inv c60k 60 nsec constant clock e60 le60inv c60k The remainder are basically the result of ...

Page 104: ...es are pennanently enabled by connecting the output control at pin 1 to a pulldo l1 14 4 U401 Flip Flops 14 5 U402 Flip Flops U401 flip flops issue synchronized versions of cs2 and cs3 Then processor address strobe p_as is asserted the first positive going edge of c60 clock asserts cs2 from pin 5 of U401 This cs2 output is used as an input for the second flip flop on the next positive edge of c60 ...

Page 105: ...15 Pal U408 Pal U408 107 15 1 Pinout ofU408 PAL 107 ...

Page 106: ...to decode and generate the followinf signals o cintberr o cpavec o G cs3 o elr Pinout ofU408 PAL is U408 Pinout es3 lint berr Ip avee les4 lb freeze el00 Ir elr gnd 1 p a 1 20 vee 2 19 leintberr 3 18 lepavec 4 17 Ig es3 5 16 leIr 6 15 7 14 8 13 9 12 10 11 107 Rev 1 of 10 May 1987 CO FIDE TlAL ...

Page 107: ...16 Sun 3 Memory Management Unit MMU Sun 3 Memory Management Unit MMU 111 ...

Page 108: ...st of it lies in secondary memory devices such as disk and tape drives To access this memory virtual addresses from the processor or DVMA devices must be translated into physical addresses To envision this address space imagine the virtual address as 32 bits from the processor each with its own 3 bit context contexts are also called processes This translation ofvirtual addresses into physical addr...

Page 109: ...13 another 4 bits of address o Each context contains 256 Mbytes A27 17 another 11 bits of address This total of 28 address bits defines virtual address space The figure below illustrates this progression from context to segment to page to individual byte location Figure 16 2 Sun 3MMU bit A30 A28 Context Register 8 conlexts process size 0 256 Mbyres bit A27 AI7 Segment Map 2048 per process 128 Kbyl...

Page 110: ...17 Context Register U509 Context Register U509 115 17 1 U509Pinout 116 17 2 U509 Input Signals 116 17 3 U509 Output Signals 117 ...

Page 111: ...l Address ctxt 2 0 A27 17 A16 13 A12 00 A30 28 2K Segments 16 pages 8 Kbytes 8 Contexts per context per segment per page L J The context register has read and write controls rd_ctxt and wr_ctxt but no initialization Table 17 1 U509 Context Register Description NAME A 31 28 SIZE TYPE CONTEXT REGISTER Ox3 BYTE R W The U509 context register is actually a PAL that holds the current usrlsupervisor cont...

Page 112: ...a 1 20 vee ti dO 2 19 nu19 ti d1 3 18 ctxtO ti d2 4 17 to dO ti d3 5 16 to dl len bex 6 15 to d2 b a28 7 14 to d3 b a29 8 13 etxt1 b a30 9 12 etxt2 gnd 10 11 rd_ety Inputs to U509 PAL are en bcx TTL data bus inputs for writes to context register enable bus context from VME section of the 2060 usl r context information from VMEbus Rev 1 of 10 May 1987 C01 TIDE ilAL ...

Page 113: ...lexing between the user context presented on the V1vfEbus and the context presented on the TTL data bus inputs letxtO en_bex Ib_a28 select VME input len_bex Ito_dO select TTL daJa input letxtl en bex Ib_a29 select VME input len_bex Ito_dl select ITL daJa input letxt2 en_bex Ib_a30 select VME input len_bex Ito_d2 select ITL daJa input Generally these equations indicate that if the en_bcx signal fro...

Page 114: ... U500 08 Segment Map U500 08 121 18 1 Segment Map Read and Write Cycles 122 Segment Map RAM Read Cycle 122 Segment Map RAM Write Cycle 123 Truth Table for the U508 Buffer 123 18 2 Segment Map RAM Control Signals 123 ...

Page 115: ... 8 bit byte ing read from or written to the segment page map bus labelled ia 24 17 on page 5 of the schematics The figure below presents a simplified illustration of segment map data flow Segment Map RAM U507 00 U506 r I I I I I I I I processor address lines A27 J7 Segment Map RAM I U507 I I I from conJexl register ct a 2 0 I I I ___ J 1TLdala Segment Map DaJa inldaJa out to page map RAM Buffer U5...

Page 116: ...sabled An I O cycle to the segment map RAM begins with the RAM in a read state that is output data is present on their DIlDO pins The segment map data buffer U508 is output enabled by the gate signal mmu gtseg from U1402 Segment lap RAl 1 Read Cycle A read of the segment map RAM will start with the nonnal deassertion of the segment RAM write strobe mmu_weseg high the p2_IW signal going high then m...

Page 117: ...vated at the same time as the write enable to the RAM in order to prevent read data now automatically enabled onto the ia 24 17 bus when the RAM chips go from write to read from conflicting with the buffer s write data also enabled onto the bus In other words you can t have the RAMs enabling data onto the bus at the same time as the buffer enables irs data onto the bus 18 2 Segment l Iap RAM Contr...

Page 118: ...a 24 17 When mmu g is issued in conjunction with p2_TW being low write cycle data from the TIL bus is gated through U508 and coupled to the outputs of the segment map RAM This data is loaded into the RAM on the rising edge of mmu_weseg the deactivation of the RAM write enable signal When mmu_weseg goes high the RAM are READ out enabled but there is no conflict because the data output is the same a...

Page 119: ...19 Page Map RAM Page Map RAM 127 ...

Page 120: ...6 sections of 16 entries each Each section is pointed to by a segment map entry and is called a page map entry group or pmeg Table 19 1 Format ofa Page Map Entry A3l A Q A29 A28 A27 A26 A25 A24 A Al9 AlP AWl V W S X TYP TYP A 1 1 reserved physical 1 0 page number Table 19 2 MMU Statistics Bits Bit Meaning v valid bit implies read access w write access bit s system access bit x don t cache bit a ac...

Page 121: ... outputs by issuing the appropriate write enable strobe This tri states the page map s output pins One of the four U610 07 transceivers is then output enabled by one of the four gating signals Disabling the outputs of the RAM occurs during cs2 gating of the tran sceiver occurs later in cs4 An example of the decode of a write enable signal in this case mmu we24 is given below rnmu we24 ctlspc p_a31...

Page 122: ...of cs4 p2_rw indicates a read cycle signal is high and you have not entered the end of the read cycle ttlrdend is still high or 3 you are doing a control space access to the device decoded by address bits pa_31 28 to be the page map RAM 0001 p2_aOl 0 decode to BYTE16 01 you are in clock state four cs4 is valid you are in a write cycle p2_rw is low and you have not yet entered the end of the write ...

Page 123: ...20 Statistics Control PAL U611 Statistics Control PAL U611 133 20 1 U611 Input Signals 133 20 2 U611 Output Signals 134 ...

Page 124: ...d bit from MMU accessed bit from MMU type bits from MMU write enable strobe for control space access doing a read write operation terminate write cycle for above state clock used to time statistics updating state clock used to time statistics updating state clock used to time statistics updating state clock used to time statistics updating cycle is a legal device space cycle do update Rev 1 of 10 ...

Page 125: ...n of stat bit 0 acc updated version of stat bit o mod updated version of stat bit lnod latched version of modified bit Write strobe there are two sources of writes to the static RAM in the MMU The processor needs to be able to read write and the statistics bits must be updated when a device space cycle occurs CJ Processor writes are tenninated with ttlwend since the decode path for we24 is quite s...

Page 126: ...Chapter 20 Statistics Control PAL U611 135 Ilmod latched version ofmodified bit Ilmod i_mod p2_rw I cs 4 set ifwrite or already set Ilmod cs4 hold as long as cs4 Rev 1 of 10 May 1987 CO FIDEl lAL ...

Page 127: ...21 wlMU Validation and Decode PAL IJ612 M 11J Validation and Decode PAL U612 139 21 U612 Input Signals 139 21 2 U612 Output Signals 140 At w K ij ...

Page 128: ...2 are rrunu s rrunu w rrunu v cs4 cs4 5 devspc 139 type bits etermine physical address space page is supervisor access only page is writable page is valid read write cs4 output of MMU is stable by now cs4 5 feedback is stable freeze doing a device space physical address cycle function code 2 doing a supervisor cycle used to end cycles especially for mmu_ram Rev 1 of 10 May 1987 CO BDEl llAL ...

Page 129: ..._as end ofcye e This is done because the the type bits may glitch during statistics updating mmu ram mmu verr mmuyerr mmu val valid RAM cycle typeO space includes video page is invalid page is valid but protection is bad physical address cycle s protection is ok allow statistics updating The ItypO signal provides a latched version of the type O bit for VME dsack signals input to U204 dsack PAL lty...

Page 130: ...ted Table 21 2 Truth Table for MMU Protection Bits Inputs Outputs Meaning Status I de spc mmu_v p2_f mrnu_w p23c2 mmu_s mmu_verr mmu J eIT mmu_val 1 0 0 1 not device space cycle I 0 0 1 0 1 page is marked invalid READS I 0 1 1 0 0 0 0 usr supv usr 0 1 1 0 1 0 1 1 usr supv ERROR 0 1 1 1 1 0 0 0 supv supv WRITES 0 1 0 0 0 1 1 usr sUP ll ERROR prot 0 1 0 1 0 0 0 0 usr supv usr 0 1 0 1 0 1 0 1 1 usr s...

Page 131: ... mmu w mmu_s devspc mmu v mmu w p2_fc2 These basic equations are used for mmu_val mmu_vme mmu_io and mmu_ram They are funher qualified by clock edges cs4 cs5 and also by type space decode bits typ 1 0 rnrnu_verr cs4 qualified by cs4 rnrnu_perr devspc rnrnu v cs4 devspc Immu_v qualified by cs4 mmu w Immu_s I Rev I of IOMay 1987 CO iFIDE lAL ...

Page 132: ...2_fc2 Enabled at s4 andJrozen at n VME cycles are type 2 or 3 Signal is held valid till cycle ends indicated by deassertion ofp2_as mmu vrne p2_as cS4 cs4_5 devspc mmu v p2_rw Immu_s typl p2 as cs4 cs4_5 devspc mmu v p2_rw p2_fc2 typl p2_as cs4 cs4_5 devspc mrnu v ITUn J W Immu_s typl p2 as cs4 cs4_5 devspc mrnu v mrnu w p2_fc2 typl p2_as mrnu VIne hold through end ofcyc e Rev 1 of 10 May 1987 CO ...

Page 133: ...l typO p2_as cs4 cs4 5 devspc mmu v mmu w mmu s typl typO p2_as cs4 cs4 5 devspc mrnu v mrnu w p2_fc2 typl typO p2_as mrnu io The mmu_ram signal is not qualified by cs4 it is sampled by the memory CAS decoder and the video interface harcfv are RAM cycles are type 0 mrnu ram p2_as devspc mrnu v p2_rw mmu s typl typO p2_as devspc mmu v p2_rw p2_fc2 typl typO p2_as devspc mmu v mmu w mmu s typl typO ...

Page 134: ......

Page 135: ... 22 P2 Bus Control and Address Buffers P2 Bus Control and Address Buffers 147 22 1 U700 Comparator 147 22 2 U703 01 P2 Address Buffers 147 22 3 U704 Control Signal Buffer 148 22 4 Aliases 148 ...

Page 136: ...t32M is issued This signal is used in the 3104 CAS decoder PAL as indication that an access is is being made to the bot tom 32 Mbytes Input to the comparator is permanently enabled by the connection of a pulldown to pin 1 the gating signal The table below summarizes the logic U700 Comparator Inputs Output G Input enable mmu a 31 25 p2 bot32M Low All low equal GND Low Low High not equal to GND High...

Page 137: ...own Signals buffered by U704 are a mmu_a 24 upper lower 32 Mbyte select bit a p_fc 2 unbuffered high order function code bit from the processor a c62 62 nsec clock from the 16 MHz crystal on page 25 of the schematics U2505 This signal is available only if12502 is IN a refr refresh signal from U2409 DVMA controller o p_siz 1 0 unbuffered processor size bits indicating the size of the data to be tra...

Page 138: ...ity Control and Parity Check PALs U802 and U812 152 23 5 U812 Parity Check PAL 153 U812 Input Signals 153 U812 Output Signals 153 23 6 U802 Parity Control PAL 156 U802 Input Signals 156 U802 Output Signals 157 Pinout ofU802 PAL 159 23 7 Memory Error Register U801 161 23 8 Byte Select Buffer and Address Bit Driver U813 162 23 9 Parity Data Buffer U3112 162 ...

Page 139: ...t byte of address bits 15 8 from U8IO o rd pad l6 outputs the next highest byte of address bits 23 16 from U809 o rd pad 24 outputs the high order byte of address bits 31 24 from U808 U808 also latches up the three context bits for use by the MMU in translating this virtual address to an physical address Finally U808 latches up the s_dma signal indicating whether or not a DMA cycle was being execu...

Page 140: ...a write cycle the inputs at port B are selected for transmission In this case a write cycle asserts the P2 parity byte select bits p2_par 24 16 08 00 from U801 memory error register These two PALs work in tandem U812 looks at the parity check bits from the parity checkers the size and offset bits from the processor and asserts CJ a parity error signal parerr if appropriate CJ a VMEbus error signal...

Page 141: ... U812 parity check PAL are derived below sample par_err 24 The first term of the above equation says that the parity error signal for the most significant byte D 31 24 is asserted when the sample signal is not true not in state cs8_csO offset bits indicate 0 byte offset and the parity check bit comes from the high order data byte p2_d 31 24 The second term of the above equation is a self latching ...

Page 142: ...mple p2_sizl p2_sizO p2_aOO par_dOS longword transfer 0 or 2 byte offsets sample p2_sizl p2_sizO p2_aOO par_dOS 3 byte transfer 0 or 2 byte offsets sample p2_sizl p2_aOl p2_aOO par_dOS 1 or 3 byte transfers 1 byte offset sample p2_sizO p2_aOl p2_aOO par_dOS Word or longword transfer 1 byte offset sample p2_aOl p2_aOO par_dOS 2 byte offset sample par_err OS self latching The first five tenns indica...

Page 143: ...2_sizO p2_aOO par_d24 par_d16 par_d08 par_dOO vrneberr p2_sizl p2_sizO Ip2_aOl p2_aOO par_d24 par_d16 vrneberr p2_sizO p2_aOl p2_aOO par_dOB par_dOO vrneberr p2_sizl p2_sizO p2_aOl p2_aOO par_d24 vrneberr p2_sizl p2_sizO Ip2_aOl p2_aOO par_d16 vrneberr p2_sizl p2_sizO p2_aOl p2_aOO par_dOB vrneberr p2_sizl p2_sizO p2_aOl p2_aOO par_dOO sample vmeberr All the parity errors are ORed together into on...

Page 144: ...s o latch strobe for the four parity address registers par_as and o the sample signal which tells U812 when to check for parity errors Inputs to U802 PAL are Parity Interrupt Enable from memory control reg allows software to selectively enable or disable the parity interrupt Parity Check Enable from memory control reg indicates whether you are in parity check or parity generation devspc pad24 pare...

Page 145: ...nals are given below The first is rd_pad24 pa J2A valid rom U14011TLBus decoder during a read cycle A state diagram illustrates the derivation of the remaining three signals sample par_as and par_irq First the states of the state diagram are Parity State Diagram Suue Values Control State Bits State q2 ql qO 0 0 0 nuO 0 0 1 nul 0 1 0 freeze 0 1 1 sendresults 1 0 0 nu4 1 0 1 genparity I I 0 latchpar...

Page 146: ...ate 1 not used freeze Parity error freeze latch and parity check bits sendresults Parity Qlecker sends back the results of check nu4 State 4 not used genparity Parity Checker generates parity check bits latchparity Up address and tell Parity Checker to check idle Not enabled Not a read Not acknowledged Not devspc access Rev 1 of 10 May 1987 COl TIDE IIAL ...

Page 147: ... 159 Pinout of the U802 PAL is U802 Pinout e60 1 par_ien 2 par_chic 3 ll p2_r 4 F2 aek 5 tr devspe 6 w 1t Ipad2 7 nuB 8 Ipa err 9 gnd 10 pal 20 vee 19 nu19 lB q2 17 16 q2 wx 15 par_irqk 14 pa as 13 Isa e 11 12 Ird_pad24 11 loe Rev 1 of 10 May 1987 CO FIDE TL L ...

Page 148: ... U802 Parity Control PAL State Diagram 111 IDLE else c60 par_chIc p2_fW p2_ack devspc else c60 101 GENPARITY sample 0 c60 else else par_chIc pad24 p2_rw 011 SENDRESULTS sample 0 parerr c60 else j al w a s 1 100 I I not wsed L J j al w a 001 I nol wsl d I I I L J r al w a 000 I not wsl d I I I L J Rev 1 of 10 May 1987 CO rmENTIAL ...

Page 149: ...ble level 7 interrupt par_irq qO pad24 p2_rw qO parerr par_ien ql par_chk q2 The memory error register provides the necessary control and information to deal with parity errors It stores information on which byte s caused the parity error sets a pending parity error intenupt and provides functions to test parity error checking o When rd par signal is asserted the four parity control bits are enabl...

Page 150: ...ted on all memory write cycles o Parity interrupt enable enables level 7 interrupts if a parity error is detected Remember level 7 interrupts are non maskable o Parity interrupt is true if a parity interrupt is pending 23 8 Byte Select Buffer and Address Bit Driver U813 23 9 Parity Data Buffer U3112 Only half of this ALS240 buffer is actually used in the parity circuitry the four parity error byte...

Page 151: ...U901 MOS Read Write Control 172 U901 SCC Interrupt SYNCWAIT State 176 24 3 U904 MOS Read Write Strobe Decoder 179 U9 4 Pinout 179 USX 4 Input Signals 180 U904 Output Signals 180 24 4 U902 MOS Write and U903 MOS Read Buffers 184 U9 2 MOS Write Buffer 184 U9 3 MOS Read Buffer 184 24 5 MOS Read and Write Cycles 185 MOS Read Cycle 186 MOS Write Cycle 186 24 6 Mouse and Keyboard SCC 186 U405 and U2207 ...

Page 152: ...ve Data Pam 187 24 7 Serial Pons A and B ttya and ttyb 187 rransmit Data Path 188 Receive Data Pam 188 24 8 EEPROM and EPROM 188 EEPROM 190 EPROM 190 24 9 rime of Day TOD Oock 190 rOD Oscillator Circuit 190 ...

Page 153: ... Device Address bits Address KEYBDMOUSE p2_a20 p2_aI9 p2_aI8 p2_aI7 Ox00000o SERIALIO p2_a20 p2_aI9 p2_aI8 p2_a17 Ox020000 EEPROM p2_a20 p2_aI9 p2_aI8 p2_aI7 Ox040000 TOD p2_a20 p2_a19 p2_a18 p2_a17 Ox060000 EPROM p2_a20 lp2_aI9 p2_a18 p2_a17 Ox100000 You can access the MOS bus using one of three cycles 1 MOS read cycle or 2 MOS write cycle or 3 Diagnostic cycle Each of these accesses are defined ...

Page 154: ...les PAL NOTE U900 is the first level decoder for the MOS devices Its outputs function as fol lows o moswren this low active signal enables the write data buffers U902 for the MOS devices The DCP is not included This signal also starts the dtack state machine and indicates to U904 whether you are in a read or a write cycle A write to the EPROM is available to enable diagnostics to check the statist...

Page 155: ...the state of the P2 read write signal p2_rw A low indicates a write cycle high indicates a read cycle When the mmuio signal on pin 8 of U900 is pulled low active the P2 address bits A20 A17 will decode to a TYPEl space indicating an I O device MOS device When p_a 3l 28 are all high and the Control space signal ctlspc is active this indicates a diagnostic cycle bypassing the MMU When the mmuio sign...

Page 156: ...ned and address bits A28 A31 are high or 3 a diagnostic write cycle to the EPROM a write to the EPROM is essen tially a write to a bit bucket The diagnostics write cycle enables diagnos tics to check statistics logic without actually affecting any devices LJ900 l 10S Read Enable mosrden r j I mosrden p2rw p2as mmuio p2a20 p2a19 p2rw p2as mmuio p2a20 p2a19 p2a18 p2a17 p2rw p2as cntlspc pa31 pa30 pa...

Page 157: ...k the software is supplied a vector by the intenupting controller Diagnostic C ele cliagc diagcy p2as cntlspc pa31 pa30 pa29 pa28 p2rw p2as sccack diag sec access sec vect d int 24 2 U901 MOS SACK State Machine diagcy is issued on pin 13 of U900 by one of the following two events 1 serial controller access bypassing the MMU P2 address strobe is asserted control space ctlspc is asserted and address...

Page 158: ... e60 I 1 20 Vee I moswren_ I 2 19 msaek I mosrden I 3 18 qO seeaek 4 17 q1 init I 5 16 q2 I es4 I 6 15 etO I p2as_ I 7 14 et1 I I 8 13 et2 I I 9 12 stroben I GND I 10 11 oe I I NOTE For the ollowing explanation see the MOS Bus read cycle timing diagram in the appendix The following figure illustrates the MOS control state machine Rev 1 of 10 May 1987 COl rIDENTlAL ...

Page 159: ...ben 1 p2as Imsack p2as stroben 1 else msack I stroben 1 moswren mosrden sccack cs4 msack I stroben 1 count 5 __ Imsack I stroben 0 count 5 rnsack I stroben 0 else There are two paths through the MOS control state machine 1 MOS read write and 2 see interrupt Rev 1 of 10 May 1987 CONFIDENTIAL ...

Page 160: ...llowing two tables U901 Control Counter States Control State ICounter Value q2 ql qa idle I 1 1 syncwait 1 a a mosstroben 1 1 a mosend a 1 1 nostatea 0 0 0 nostatel 0 0 1 nostate2 0 1 0 nostate5 I 0 1 U901 Wait Counter States Control State Counter Value ct2 ctl ctO cntO 0 a 0 cntl 0 0 1 cnt2 0 1 0 cnt3 0 1 1 cnt4 I 0 0 cntS 1 0 I cnt6 1 1 0 cnt 1 1 1 Note that so e of the states in the control sta...

Page 161: ...roben h h state nostate1 goto idle msack hi stroben h goto idle state nostate2 msack stroben_ hi h state nostate5 goto idle msack h stroben_ h goto idle U90l is set to the IDLE state at initialization and the control counter is set to 111 If you look at the MOS read timing diagram you will see that msack and stroben are false high during IDLE This is also illustrated in the state diagram equation ...

Page 162: ...ait else if moswren_t mosrden_ cs4_ sccack then mosstroben else idlei In MOSSTROBEN state the control state counter goes from 111 IDLE to 110 MOSSTROBEN Remember when the least significant bit qO of the control state counter goes from one to zero it enables the wait state counter et2 ctO to begin incrementing unless or until the signal cnten goes high resetting this counter Once in MOSSTROBEN stat...

Page 163: ...et cntreset cntreset cntreset c60 cntreset As long as the wait state counter is less than 5 101 U901 remains in MOSSTROBEN state When the count reaches five 540 nsecs into the MOS read write cycle U901 enters MOSEND state This is designated by 011 in the control state counter Rev 1 of 10 May 1987 COSFIDEl T AL ...

Page 164: ...strobe When the p2as signal goes high msack also goes high still pacing p2as On the next clock you reenter IDLE state If you look at the timing diagram MOS bus cycle begins in the IDLE state with both msack and stroben high IDLE state continues until 180 nsecs into the cycle S5 of cOO clock MOSSTROBEN state continues until count 5 540 nsecs into the cycle at which time U901 enters MOSEND state Whe...

Page 165: ...low 1 synchronization to PCLK baud rate clock on the serial communication con troller 205 nsecs 2 the daisy chained interrupt enable output from the first SCC chip to get out of the chip 250 nsecs and 3 the interrupt enable input to set up in the next chip 100 nsecs In other words these seven wait states give the two SCCs time to decide which of the SCCs will issue the interrupt At this point the ...

Page 166: ...ates is IDLE SYNCWAIT MOSSTROBEN MOSEND o to 180 nsecs until 660 nsecs until 1020 nsecs until 1200 nsecs at which time you go back to idle Thus the interrupt acknowledge cycle for the MOS devices is 1200 nsecs long MOS devices have very slow output disable times A write cycle to a MOS dev ice following a read cycle will cause a buffer conflict unless time is allowed at the end of a read cycle for ...

Page 167: ... read write keyboard and mouse Cl read write EEPROM and Cl read EPROM The read strobes for the 8530 SCC devices are active for nonnal reads and inter rupt acknowledge cycles In addition to nonnal accesses the serial port SCC read and write strobes are active during a diagnostic cycle A diagnostic cycle access bypasses the MMU is mapped into Control space as UART Bypass so that diagnostic programs ...

Page 168: ...ouse interrupt acknowledge Cl linit resets the SCC s Description of the output signals Cl rd_eprom read EPROM boot Cl rd_eeprom read EEPROM Cl wr_eeprom write EEPROM Cl rd_keybdm read keyboard mouse scc Cl Iwr_keybdm write keyboard mouse scc Cl Ird_serial read tty ab scc Cl Iwr_serial write tty ab scc Cl Ird_tod read TOD chip Cl Iwr_tod write TOD chip Cl mos_aO address bit AD on the MOS bus is gat...

Page 169: ...RD EPROM IO bootcy VALIDRD This equation explains how to get access for a read of the EPROI 1 To access it you must be in a valid read cycle defined above address bits A20 17 must decode to the EPROM in TYPEl space OxlOOOOO and you must be in an I O cycle or you must be in a booteycle with a valid read cycle The remainder of the outputs are defined below r_d_ _e_e_p_r_o_rn_ V_A_L_I_D_RD_ _E_E_P_R_...

Page 170: ...ead cycle have the TYPE1 space address for the keyboard mouse KEYBDMOUSE OxOOOOOO and you must be in a valid I O cycle Or you can access it through an interrupt acknowldge cycle sccack and valid read of the interrupt vector VALIDWT KEYBDMOUSE IO reset A write to the keyboard mouse is similar except that there is no valid write dur ing an interrupt acknowledge cycle rd serial VALIDRD SERIALIO IO VA...

Page 171: ...read r_d_ _t_O_d V_A_L_I_D_RD_ _ _O_D_ _I_O Notice that the TOO clock can only be accessed through the 1v11vfU no diag nostic cycle VALIDWT TOD IO mosrden TOD IO p2_aOO moswren TOD IO p2_aOO The AD bit is gated through U904 to reduce the number of transitions coupled to the TOO clock Transitions coupled to the oscillator circuit cause the TOO clock to run fast to control this mos_aD is gated throu...

Page 172: ...p used to minimize undershoot to its con nected MOS devices When moswren from U9OO goes active data from the P2 data bus is coupled to the MOS data bus U902 MOS Write Data Buffer P2 data bus U902 MOS data bus write data buffer direction moswren On the rising edge of cnten data from the MOS bus m_d 7 0 are latched onto the P2 data bus The cnten signal is also the LSB qO of the control state counter...

Page 173: ...g cycle to make certain that the MOS device has had time to clear itself of any read data 2 When you do a status read from any of the 8530 serial communication con trollers the data is not guaranteed to be stable in the SCC s status register for the entire length of the MOS read cycle This is because status registers in the SCCs are updated asynchronously and there is no provision for latch ing th...

Page 174: ...dress strobe p2_as goes high the read cycle reenters IDLE state The MOS write cycle is much like the MOS read cycle The MOS write cycle starts out in IDLE state with the control state counter in U904 set to 111 Both msack and stroben are high false When mosrden stays false high and moswren goes low true a write cycle is signalled cs4 dropped at 120 nsecs and ccack stays high false since this is no...

Page 175: ...across the mouse and keyboard data outputs to slow the transmit signal s edge rate to between 1 and 2 microseconds this reduces radiation RX data enters the 2060 board on pin 1 keyboard and pin 5 mouse of JI000 Receive data lines are linked to 4 7 K Q pullup resistors necessary because the mouse uses open collector circuitry and then connect to U1002 differential receiver with hysteresis The inter...

Page 176: ...rt connectors 11100 and 11101 The data and control lines are linked to Ul003 1 differential receivers with hysteresis this internal hysteresis circuitry provides noise immun ity The plus inputs are connected to ground and the signals enter the minus inputs this inverts the signals NOTE This inversion means that the control signals are by default ACTIVEI The 4 7 Kn resistors connected serially to t...

Page 177: ...cycle AND 2 a MOS read cycle AND 3 strobe enable is true MTD 4 it s not a reset cycle Read of and write to the EEPROM are defined similarly rd_eeprorn mosrden stroben reset p2_a20 p2_a19 p2_a18 p2_a17 bootcy diagcy wr_eeprom moswreh stroben reset p2_a20 p2_a19 p2_a18 p2_a17 bootcy diagcy Both the EEPROM and the EPROM use addresses directly from the processor p_a addresses virtual addresses and not...

Page 178: ...used J1200 is jwnpered The table below gives this configuration Table 24 4 EPROM Jumpering EPROM Size Jumper IN or OUT J1200 J1201 256K IN OUT 512K OUT IN The rd_eprom line has a 180n series termination resistor R907 to handle undershoot 2 t9 Time of Day TOD Clock TOD Oscillator Circuit The TOO clock is controlled by an Intersil 7170 real time clock chip Its 8 bit bidirectional data bus is connect...

Page 179: ... aroWld 3 volts The TOO interrupt is issued at pin 12 of the 7170 chip The low active interrupt signal int is connected to a 4 7 K pull up resistor inverted through UI104 inverter with hysteresis t The signal is then connected as clock to the two inter rupt flip flops U1205 1 and U1205 2 U1201 2 top flip flop on extreme right of page 12 of the schematics is interrupt request level 7 flip flop U120...

Page 180: ...ice Decoder 204 U1401 Pinout 205 U1401 Input Signals 205 Output Signals of the U1401 PAL 206 25 U1402 MMU Decoder 210 U1402 Pinout 212 U1402 Input Signals 212 U1402 Output Signals 213 25 5 U1403 Miscellaneous CPU Signal TTL Bus Decoder 218 Pinout ofU1403 PAL 219 U1403 Input Signals 219 U1403 Output Signals 220 25 6 Ethernet Control Register 223 U1405 Ethernet Control Write Buffer 223 U1407 Etherne...

Page 181: ...25 8 U1410 Diagnostics Register 225 25 9 U1409 ID PROM 225 25 10 U1404 P2 to TTL Data Buffer 225 25 11 U2905 and U2906 User DVMA Enable Register 226 25 12 U203 Bus Error Register 226 25 13 U509 Context Register 226 U509 Pinout 227 Inputs and Outputs of U509 Context Register 227 ...

Page 182: ...ls from Ul400 PAL These synchronous signals are the read and write END sig nals Thus the beginning of an I O cycle is not dependent upon U1400 but the end of the cycle is dependent This PAL controls the TTL bus transceiver and generates the TTL bus dsack sig nal labelled tsack q2 qt and qO are the dsack state machine control counter bits The other combinatorial output is ttlbfen the TTL bus data t...

Page 183: ...t of the TIL buffers o tsack synchronous interrupt acknowledge for the TIL bus o ql ttlrdend signals the end of the TIL read cycle this signal is coupled to the ql bit of the state machine s internal control counter o qO ttlwend signals the early end of the TIL write cycle this signal is cou pled to the qO bit of the state machine s internal control counter For the following description please con...

Page 184: ...0 19 A17 decode to either the parity error or Ethernet controller registers in TYPE1 address space or 4 TIL buffer s output is enabled ttlbfen stays low untilTILE1 cTI state q1 bit goes low This self latching mechanism is necessary to enable the out put of the TIL buffer U1404 until the end of the bus cycle because cs4 deactivates during TILWREND state tsack q2 qO p2as q2 ql sanity p2as The tsack ...

Page 185: ...l state counter bits are derived from the equations above States defined for U1400 state machine are TTL Bus DTACK State l lachine Diagram ttlend nostatel ttlwrend ttlwait nostate4 nostate5 nostate6 idle end of TTL bus cycle not used state 1 write strobe dissable TTL bus wait state not used state 4 not used state 5 not used state 6 idle state Rev 1 of 10 May 1987 CONFIDESTIAL ...

Page 186: ...Figure 25 2 Chapter 25 TIL Bus Accesses 199 TTL Bus DTACK SACK State Machine Diagram c60 tsack 1 Rev 1 of 10 May 1987 COl TIDENTlAL ...

Page 187: ...ntrol state counter at 111 q2 ql and qO 111 In IDLE state the interrupt acknowledge signal tsack remains high inactive IDLE is defined as state idle No valid ITL bus access ail here in idle sanity state idle else tsack power on reset 1 ttlbfen state t tlwait valid ITL bus access golo wait Slale tsack 1 else always state idle tsack 1 no valid cycle stay in idle When ttlbfen goes low actually on the...

Page 188: ...ou look at the timing diagram you will see that this occurs 245 to 255 nsecs into the bus cycle The tsack signal is still pacing address strobe still low because the acknowledge signal must stay valid until address strobe is deasserted TTLWREND issues an early end to the write cycle necessary to guarantee that the data and address hold times are met The ttlwrend signal is connected to U1403 1 to d...

Page 189: ...ned as state ttlend This is the last state in the TTL bus cycle Here both ttlwend and ttlrdend are active sanity state idle tsack 1 always state idle tsack p2as power on reset cycle over go back to idle On the next c60 clock you re enter IDLE state The tsack signal remains high inactive Unused states are defined below Not used states Do not go here Ifyou get here on a power on reset leave immediat...

Page 190: ...s through the MMU labelled ttlbfen mmu 2 When ttlbfen occurs during cs4 the state machine enters TILWAIT state on the next negative edge of c60 clock s5 3 The tsack signal drops low 190 to 220 nsecs into the cycle 4 On the next clock s7 245 to 255 nsecs into the cycle ttlwend goes true low The cs4 signal goes high 5 On the next clock s9 ttlrdend goes active 305 to 315 nsecs into the cycle Now both...

Page 191: ...ter bits 08 to 15 And so on Byte Selection in Parity Address Selection Term Address Bits Signal Enabled Al AD BYTE24 0 0 pad24 BYTE16 0 1 rd padl6 BYTE08 1 0 rd_pad08 BYTEOO 1 1 rd_padOO In order to insure data and address hold times the ttlwend signal is incorporated into the p2_rw mrnuio ttlwend definition so the write strobes go inactive before the end of the bus cycle The devices for whom this...

Page 192: ...4 22 Irdyad16 21 Ird_pad08 20 Ird_padOD 19 Iwr ether 18 Ira ether 17 Iwr i t 16 Ira int 15 Iw _par 14 Iro_pa 13 nc Itt1wena 1 Ittlraend 2 p2_rw 3 Immuio 4 p2_a2D 5 p2_a19 6 p2_a18 7 p2 a17 8 p2 a02 9 p2 a01 10 1r p2_aOO 11 gnd 12 U1401 Input Signals Inputs to the U1401 PAL are Rev 1 of 10 May 1987 COSFIDE TIAL ...

Page 193: ...one of five bytes of the parity error and address registers There is a single byte of parity error register and there are four bytes of parity address which are decoded as follows X means Don t Care Table 25 3 Byte Decode ofthe Parity Error and Address Registers Address bits Signal Register A2 Ai AO Enabled Selected 0 X X rd paror parity error wr_par U80I and U8I3 I 0 0 pad24 parity address U8II 0...

Page 194: ...68020 s dynamic bus sizing capability to execute four successive reads of the 32 bit parity address off the 8 bit TIL bus rd ether p2_rw mmuio ttlrdend p2_a20 p2_a19 p2_a18 p2_a17 This signal is the read strobe to the Ethernet control register U1407 The signal simultaneously clocks and enables output from the Ethernet controller onto the TIL data bus To assert rd_ether you must be in a read cycle ...

Page 195: ...e interrupt register U300 The signal clocks data from the TTL bus onto the data inputs of the priority encoder U302 and the interrupt enable bus To assert wr_int you must be in a write cycle p2_I W low accessing the device through the MMU mrnuio true must NOT be in TILWREND state ttlwend must NOT be low and have selected the ethemet control register via bits A20 17 which is equal to OxOAOOOO in TY...

Page 196: ......

Page 197: ...To assert pad24 you must be accessing the device through the MMU mmuio true must NOT be in TTLEND state ttlrdend must NOT be low and have selected the parity register via bits A20 17 which is equal to Ox080000 in TYPEl space and the p2_a02 0 address bits must be equal to 100 BYTE24 tenn in the PAL listings rd pad16 p2_rw mmuio ttlrdend p2_a20 p2_a19 p2_a18 p2_a17 p2_a02 p2_aOl p2_aOO This signal g...

Page 198: ...ess bits must be equal to 111 BYTEOO tenn in the PAL listings NOTE There are a pair of generic signals ne in each timing digram which stand for the read and write strobes issued by U1401 The generic read signal is ttlspcrden on the TTL BUS READS timing diagram the generic write signal is ttlspcwren on the TTL BUS WRITES timing diagram 25 4 U1402 i 1 IU Decoder This PAL generates the page and segme...

Page 199: ...mu_we24 BYTE16 0 1 mmu_we16 BYTE08 1 0 mmu_we08 BYTEOO 1 1 mmu_weOO Finally in order to insure data and address hold times the ttlwend signal is incorporated into the p2_rw ttlwend definition so the write strobes go inactive before the end of the bus cycle _ _I_T_E__ _p_2 r_w_ _ _t_t_l_w_en_d J Rev 1 of 10 May 1987 CO rIDEl TIAL ...

Page 200: ... etlspe 2 es2 3 es4 4 p2_rw 5 p a31 6 w p a30 7 p a29 8 p a28 9 p2_aOl 10 p2_aOO 11 gnd 2 p a 1 24 vee 23 mmu we24 22 mmu_gt16 21 mmu_gt08 20 mmu_gtOO 19 hn nu gt24 18 mmu we16 17 mmu we08 16 mmu weOO 15 mmu_gtseg 4 mmu_weseg 13 ttlrdend U1402 Input Signals Inputs to the U1402 PAL are Rev 1 of 10 May 1987 CONFIDE TlAL ...

Page 201: ...Outputs from the UI402 PAL are mmu_gt24 gate buffer for byte 0 of page map prot and id bits mmu_gt16 gate buffer for byte 1 of page map page 18 16 mmu_gt08 gate buffer for byte 2 of page map page 15 8 mmu_gtOO gate buffer for byte 3 of page map page 7 0 mmu_we24 write enable byte 0 of page map prot and id bits mmu_we16 write enable byte 1 of page map page 18 16 mmu_we08 write enable byte 2 of page...

Page 202: ...o the device decoded by address bits pa_ 31 28 to be the page map RAM 0001 p2_a901 0 decode to BYTE24 00 you are in clock state four cs4 is valid you are in a write cycle p2_rw is low and you have not yet entered the end of the write cycle ttlwend is false ctlspc p_a31 p_a30 p_a29 p_a28 p2_aOl p2_aOO p2_rw cs4 ctlspc p_a31 p_a30 p_a29 p_a28 p2_aOl p2_aOO cs4 p2_rw ttlwend This signal gates the buf...

Page 203: ...E08 10 you are doing a read cycle p2_rw is high and you are in clock state four cs4 is valid or 2 mmu 8 is asserted this is the self latching mechanism needed to extend this read cycle beyond the deassertion of cs4 p2_rw indicates a read cycle signal is high and you have not entered the end of the read cycle ttlrdend is still high or 3 you are doing a control space access to the device decoded by ...

Page 204: ...2_rw ttlwend cs2 This signal mmu_we24 is the write enable for byte 0 of the page map RAM It is active when you are doing a control space access ctlspc true to the page map RAM pa_ 31 2S 0001 the p2_a OI oo address bits decode to BYTE24 00 you are in a write cycle p2_rw is low you have not ended the write cycle ttlwend is high false and you are in clock state two cs2 is true mmu we16 ctlspc p_a31 p...

Page 205: ..._a31 p_a30 p_a29 p_a28 p2_rw cs4 ctlspc p_a31 p_a30 p_a29 p_a28 cs4 p2_rw ttlwend This signal mmu g gates the buffer for the segment map R A 11 It is active when 1 you are doing a control space access ctlspc true to the segment map RAl 1 pa_ 31 28 0010 and you are in a read cycle p2_rw is high during clock state 4 cs4 is true or 2 mmu eg is true this is the self latching tenn ensuring that this re...

Page 206: ...d Segment Map RAM Of special note are two signals 1 the ttlwend signal which is used to disable the write strobes before the end of the bus cycle to insure data and address hold time and 2 the ttlrdend signal which disables the read strobes so there is no end of cycle buffer conflict The read output strobes are latched inside Ul403 since cs4 ends earlier than the read cycle The Control Space devic...

Page 207: ...nout Ittlwend 1 P a 1 24 vee letlspe 2 23 tdO Ittlrdend 3 22 Ird id les4 4 21 Iwr_diag p2_rw 5 2C Iw _syse p a31 6 19 Ire_syse p a3C 7 8 Iwr 1 s e 1Ir p a29 8 7 I d us e p a28 9 16 Ire be r Iwa cl oog 10 15 I d ctx ne 11 4 e x 1f gnd 12 13 r e Input signals to the U1403 PAL are Rev 1 of 10 May 1987 CO FIDENTIAL ...

Page 208: ...read strobe for the system enable reg wr_sysen write strobe for the system enable reg rd_usren read strobe for the user DVMA enable reg wr_usren write strobe for the user DVMA enable reg rd_berr read strobe for the bus error reg wr_diag write strobe for the diagnostic register LEOs tdO m watchdog readback bit driver onto TTL data bus o A read cycle is defined as a cycle in which the read signal is...

Page 209: ...register 0203 by assening rd_berr this same rd_berr signal will force a read of the watchdog bit from U1403 Thus the status of the watchdog error bit is available on the TIT bus every time you read the bus error register This is derived from the following equation if rd_berr tdO watchdog This equations says that if rd_berr is true then data bit zero of the TTL bus tdO is the same state as the watc...

Page 210: ...1 28 when they are 0011 Ox3 and asser tion of the write strobe during cs4 as long as you have not entered ttlwend state ttlwend signal is high Notice that there is no self latching needed for write strobes the TIL bus write cycle ends when cs4 does thus ensuring hold times for the address and data rd_ ysen Ittlrdend This equation defines the read strobe to the system enable register at A31 28 0100...

Page 211: ...ar device which is clocked on the rising edge of the device s individual write strobe issued by U1401 TIL bus decoder PAL U1405 buffer is used for write data storage to the Ethernet controller Data at the input s to the buffer t_d 7 0D is clocked to the Ethernet controller by the rising edge deassenion ofthe wr_ether signal issued by U1401 PAL and which occurs at the end of a write cycle If you lo...

Page 212: ...ernet controller 2 e_err error signal from the Ethernet chip Since the interrupt and error signals occur asynchronously to the processor they must be s TIchronized through UI407 Data at the input s of U1407 are latched to the TrL data bus t_d 7 0 by the assertion of the rd_ether strobe from U1401 When the rd_ether strobe is high deasserted the U1407 read buffer is set to a high impedance state The...

Page 213: ...ensing a unique Ethernet address the date of machine manufacture and a checksum Additionally the ID PROM stores configuration infonnation for the machine The ID PROM is located in Control Space at address A31 28 OxO in other words Contents of the PROM are organized in the table below Table 25 5 Contents ofthe ID PROM Entry Number Contentst Length in bytes 1 Format 1 2 Machine Type 1 3 Ethernet Add...

Page 214: ... error signals to the TIL data bus Data at the input to the register is stored on the low to high transition of lberr load bus error and this data is coupled to the TIL data bus when the output enable signal rd_berr goes low When rd_berr is high the register goes to a high impedance tri state U509 Context register holds present status as either user or superviser status and multiplexes between thi...

Page 215: ...19 ti dl 3 18 etxtO ti d2 4 17 to dO ti d3 5 16 to d len bex 6 15 to d2 b a28 7 1 to d3 b a29 8 13 etxtl b a30 9 2 etx 2 gnd 10 l Ird etxt Inputs to the context register are en bcx TTL data bus inputs for writes to context register enable context bus from VME circuitry user context information from VMEbus Outputs of the context register are Rev 1 of 10 May 1987 CO rIDEl TIAL ...

Page 216: ...nally to the 13 0 inputs as represented in the PAL equations t Ito dO 0 Iti dO Ito dl Iti dl Ito d2 0 Iti d2 Ito_d3 Iti d3 These signals must be inverted because outputs of the PAL are inverted The derivation of the three context bits UCfXT2 0 is given below letxtO en bex IUCTXTO len_bex ItO_dO letxtl en_bex IUCTXTl len_bex Ito_dl letxt2 en_bex IUCTXT2 len_bex Ito_d2 For instance ctxt O is asserte...

Page 217: ...hapter 25 TTL Bus Accesses 229 1 en_bcx is true low and UCfXTO Cb_a28 address bit is also low or 2 en_bcx is NOT true en_bcx is high and to_dO TTL bus data bit 0 is low Rev 1 of 10 May 1987 CO rIDE TlAL ...

Page 218: ...2 Output Signals 237 26 4 P2 Interface State Machine U1503 U1605 07 241 U 1503 Pinout 241 U1503 Inputs 241 U 1503 Outputs 242 26 5 VARB and Video Side State Machines 242 Video Read 243 Video Write 247 Video Write Timing Diagrams A Real Example 249 26 6 U1501 Byte Decode PAL 250 U 1501 Pinout 250 U 1501 Output signals 251 U1500 Buffer and U1505 DIP 253 26 7 U1608 U1603 Video Controller 253 26 8 U 1...

Page 219: ...26 9 Frame Buffer RAM 255 26 10 ECL CircuitI 256 EeL Dock 256 26 11 Horizontal and Vertical Synch State Machines 257 ...

Page 220: ...ion is determined by the assenion of vack read data or vlatch write data signals The video refresh counter on page 17 issues the address of the location in the frame buffer which is to be output to the display It is comprised of a counter U1705 04 whose output is incremented and latched in a pair of buffers U1703 02 by either RAS row address strobe or CAS column address strobe This address is then...

Page 221: ... flip flop U1607 1 26 2 U150 1 Video Select Decoder Video memory can be located either in a physically separate frame buffer address 0xFF0000 0 or in main memory address OxOO100000 In either case it takes up 128 Kbytes The frame buffer can be read from or wrinen to directly just like ordinary memory However when a copy mode write is executed the enable copy bit from the system enable register UI40...

Page 222: ...20 7 p2a19 8 p2a18 9 gnd 10 p a 1 20 vee 19 Imb16sel 18 p2a29 17 p2a27 16 p2a25 15 p2a23 14 p2a21 13 eneopy 12 eopy16sel 11 p2a17 U1504 Input and Output signals Inputs to the U1504 Decoder are nunu_a 31 17 encopy Outputs of the U1504 decoder are COPY16se1 mb16sel Equations for the two output signals are l rb16se1 Rev 1 of 10 May 1987 CONFIDE TIAL ...

Page 223: ... is actually an OR of the mb16sel term with a copy mode enable term 26 3 U1502 Video Control Decoder The two select signals from U1504 are connected to among others the U1502 video control decoder which is a multi purpose strobe decoder The signals p2rdenO and p2rden1 are output enables to gate either obits 63 32 p2rdenO or obits 31 00 p2rdenl of the video memory onto the p2_d 31 0 data bus During...

Page 224: ... e p2as 7 14 vidw nc 8 13 vidrd nc 9 12 nc gnd 10 11 lirdenl The two video select signals decoded by U1504 copy16sel and mb16sel are connected to the U1502 video control decoder Other inputs are p2rw rmnuram read write strobe indicates you are accessing memory through the MHO bit used to select upper or lower data word from 64 bit video bus U1502 Output Signals Outputs from the U1502 decoder are R...

Page 225: ...fthe LS652 is active high rdenO must be inverted rdenO mb16sel p2rw rnmuram p2a02 cs4 rdenO p2as This equation tells us that p2rdenO the read enable strobe for the upper 32 bits of video data is issued when rdenO is issued The rdenO signal is issued when 1 the mbI6sel signal is true you are doing an access to the upper 16 Mbytes of the 4 Gbyte physical address pace you are in a read cycle p2rw is ...

Page 226: ... going to execute a copy mode write writing to both video memory and main memory Should the frame buffer be busy when you want to initiate a copy mode write vcopydet will be issued which in tum holds off the CPU from issuing a dsack until vsack is issued This ensures both video and main memory are done vsack and p2_ack have been issued to U204 DSACK PAL before you end a copy mode write vcopydet co...

Page 227: ...s true until p2as address strobe goes false This latter tenn is a self latching mechanism to make sure vidrd is not deac tivated when cs4 goes inactive When p2as goes false high this self latching mechanism is aborted vidwr copy16sel p2rw mmuram cs4 vidwr p2as Video write vidwr is active for the length of the video write cycle Note that copy16sel is used instead ofmb16sel because you can do writes...

Page 228: ... flopsU1605 and U1607 This handshaking mechanism is described below Pinout of the U1503 PAL is U1503 Pinout leGO 1 vidrd 2 vidwr 3 ne 4 busy 5 sbusy G _ leopy16 7 mb16sel 8 init 9 gnd 10 p a 1 20 vee 19 nc _ lS vlatch If 17 nc 1611 qO 11 15 q1 1 q2 _ 1311 vreq 12 Ivsack 11 gnd VIS03 Inputs Inputs to the PAL are vidrd Valid video read strobe vidwr Valid video write strobe busy Video frame buffer bu...

Page 229: ...tput vlatch is the inversion of vreq used to latch various buffer registers Take a look at the two slate machines labelled VARB and Video Side They work in conjunction with each other through a trio of handshaking signals vreq and busy sbusy A cycle begins with both state machines in IDLE states These outputs are not latched and are assocated with state as in the Moore model Rev 1 of 10 May 1987 C...

Page 230: ...signal goes active low when vidrd or vidwr and NOT busy are true indicating a processor video cycle request While in IDLE U1503 is going to receive either a video read vidrd or a video write vidwr from U1502 which signals the start of a bus cycle When either of these two signals goes active low the state machine goes out of IDLE state into a read or a write service state Let s say the signal recei...

Page 231: ... When vreq goes low and is presented to the D input of U1605 0 this flip flop is cleared at the next 40 nsec clock and the inverted output a logical high is taken from pin 6 This is the SYNC state of Video Side state diagram named because it synchronizes the vreq to the 40 nsec video clock The next 40 nsec vclk40 clocks this high through U1607 Q flip flop which asserts the busy signal at pin 6 Thi...

Page 232: ...husfar 1 a video read vidrd has been issued to U1503 2 vreq is issued by U1503 3 vreq is clocked through UI605 and then U1607 to emerge as busy 4 busy connects back to U1503 deactivating vreq 5 the VARB state machine is in RDSERVRQ state This then is the handshaking mechanism between the two state machines vreq from VARB to Video Side and busy sbusy from Video Side back to VARB Figure 26 4 Handsha...

Page 233: ...or NOT busy vsack busy vreq 1 During RDSERV state the state machine waits for the return of the NOT busy signal and the Video Side state machine to progress through BUSY to SERVICE to IDLE The vsack signal goes active when NOT busy goes true The vreq signal is still a high false When NOT busy occurs the data is stable on the bus and the state machine moves into RDEND read end state Rev 1 of 10 May...

Page 234: ... and vsack are high false When a vidwr comes into Ul503 PAL vreq is issued and clocked through UI605 0 flip flop This starts handshaking between the VARB and Video Side state machines see the description of handshaking in the Video Read section above The vsack signal is issued to end the write bus cycle Write data and address are latched on vlatch which is inverted vreq so the processor need not w...

Page 235: ...state machine returns to IDLE The busy signal is re synchronized to 60 nsec clock through flip flop U1607 1 and emerges as sbusy which is used back in U1503 VARB state machine The VARB state machine enters WRSERV by the following equation state wrserv init state idle vsack 1 vreq 1 else power on reset vidwr sbusy state wrend write done and busy so go to the write end state vsack 1 vreq 1 else alwa...

Page 236: ...is clocked through U1607 1 indicating that the video state machine is no longer tied up doing a write operation the VARB state machine returns to IDLE state idle vsack 1 vreq III 1 Should the processor start another video write cycle while in WREND state vsack and vreq are suppressed and wait states occur until the video write is done and the data address latches are available for the waiting cycl...

Page 237: ...his case vreq and vsack are not issued until the write is finished IDLE state 26 6 U1501 Byte Decode PAL U1501 Pinout Figure 26 5 This PAL generates the write strobes for the video memory 4416 rams Since the video memory is 64 bits wide va02 latched version of p2_a02 is used to select the four write enable signals wren 24 16 08 oo or wren 56 48 40 32 and accounts for the symmetry of the equations ...

Page 238: ...bits 39 32 in U1908 wren08 vwe vrw va02 vaOl vaOO vwe vrw va02 vsizl vsizO IvaOl vwe vrw va02 vsizl vsizO vaOl vwe vrw va02 vsizl vaOl vaOO The wren08 signal enables data bits 47 40 in UI907 wren16 vwe vrw va02 vaOl vaOO vwe Ivrw va02 vsizl vaOl vwe vrw va02 vsizO vaOl The wrenl6 signal enables data bits 55 48 in U1808 wren24 vwe vrw va02 vaOl vaOO The wren24 signal enables data bits 63 56 in UI80...

Page 239: ...ren40 vwe vrw va02 vaOl vaOO vwe vrw va02 vsizl vsizO vaOl vwe vrw va02 vsizl vsizO vaOl vwe vrw va02 vsizl vaOl vaOO The wren40 signal enables data bits 15 08 in U2107 wren48 vwe vrw va02 vaOl vaOO vwe vrw va02 vsizl vaOl vwe vrw va02 vsizO vaOl The wren48 signal enables data bits 23 16 in U2008 wren56 vwe vrw va02 vaOl vaOO The wren56 signal enables data bits 31 24 in U2007 Rev 1 of 10 May 1987 ...

Page 240: ... a specific read or write enable strobe to the frame buffer The video state machines perform an optional read or write access to the frame buffer memory followed by a video update read cycle The basic memory cycle consists of 16 states the state machine is clocked every 40 nsec and hence repeats every 640 nsec The following are timing diagrams for the frame buffer the first is with no CPU read wri...

Page 241: ...put enable signals for the ALS 534 output buffers connected to the frame buffer RAM These four state bits also generate through U1603 the video RAS CAS write enable horizontal clock hclk enable request enreq which qualifies the busy signal through Ul600 AND gate vack and vgen which enables read data from the video buffer RAM 26 8 U1700 01 Video RAS CAS Latches There are separate row and column add...

Page 242: ...able signal mwren 56 00 effec tively disabling mgen l 0 as an output enable The vack signal latches read data into the LS 652 transceivers vlatch latches write data into the transceivers These data are then connected either to on a read cycle or from on a write cycle the P2 data bus The video output latches between the 64 bit frame buffer data bus and the 8 bit ECL converters on page 23 are multip...

Page 243: ...onitor as every eighth pixel being slightly darker than the rest U2310 flip flop is used to shape and clean up the signal to the differential inputs of the CRT U2310 also provides the differential signals needed by the CRT to drive the mon itor R2304 and 2305 resistors are used for differential transmission and diodes 2304 01 are used for transient suppression clamp the voltage levels to 5 VDC and...

Page 244: ...vel converters is the blank signal This is the video blanking signal generated by the horizontal state machine on page 22 and qualified by the video enable signal from the system enable register on page 14 b When blank to the CS inputs of the TTL to ECL level converters is true low the outputs of the level converters are forced to a zero state black which means that nothing will be painted onto th...

Page 245: ...n is ANDed at U1600 with the enable video bit from the system enable register to disqualify blanking when both signals arc true The hsynch signal which occurs every 16 Jlsecs 1152 visible plus 448 invisible horizontal pixels times 10 nsec EeL clock clocks the vertical state machine s counter Vertical timing is given below 1 state 1 line 16 00 sec 62 50 KHz Range Lines Length Time Lines sec 1152x90...

Page 246: ... and also clears the video refresh counter on page 17 Notice that the vertical blanking signal vblank is fed from the output of the state machine register U2203 back into the horizontal state machine This causes hblank and vblank to be ORed together The horizontal state machine s blanking always occurs before vertical blanking if a vblank is valid after an hblank it will merely append the vblankin...

Page 247: ...27 VMEbus Performance VMEbus Perfonnance 263 27 1 2060 V ME Implementation 263 ...

Page 248: ...when under the control of an external VlvfE master MASTER CAPABILITIES Data Bus Size D32 MASTER 32 16 8 bit data Address Bus Size A32 MASTER DYN 32 24 16 bit addresses Timeout Option TOUT 737 737 microsecond timeout period Sequential Access None Interrupt Handler IH 1 7 STAT Levell thru 7 independently jumperable All interrupts use vectors provided by VMEbus interrupters per the VME spec Requester...

Page 249: ...onds to the top 2 Gbytes by performing DVMA using user function codes Response can be dynamically disabled on 256 Mbyte boundaries The 2060 responds to the bottom 1 Mbyte by performing DVMA by using the system function codes SYSTEM C01 OLLER CAPABll ITIES Clock Option SYSCLK 16 MHz jumperable not used on board Arbiter Option ONE Bus Request Grant Level 3 only or External Arbiter Bus Time Out Modul...

Page 250: ......

Page 251: ...POWER CHARACfERISTICS Chapter 27 YMEbus Perfonnance 265 5 Volts 5 Volts 12 Volts 12 Volts 14 Amp Max 1 Amp Max 0 5 Amp Max Not used Rev 1 of 10 May 1987 COl TIDE1 1 AU ...

Page 252: ...r and Requester 272 Transitions from BUSREQ State 273 Transitions from MASTER State 274 Transitions from MASTER_NG State 276 Transitions from BUSGRANT State 276 28 3 State Machine as Requester Only 277 Transitions from IDLE State 277 Transitions from BUSREQ State 278 Transitions from MASTER State 279 Transitions from MASTER_NG State 280 Transitions from the BUSGRAA f State 281 ...

Page 253: ...umper from J2701 to J2700 leaves the 2060 board operating only as a VMEbus requester as detailed in the VMEbus Manual The arbiter requester state machine operates differently in the two modes so they are handled separately below This entire discussion assumes a familiarity with the VMEbus specification so no attempt is made here to explain the basic work ings of the VMEbus o B_AEN Originally stood...

Page 254: ...270 2060 CPU Board Engineering Manual CONFIDE1 TIAL Rev 1 of 10 May 1987 CO BDEl IAL ...

Page 255: ...quester Figure 28 1 Chapter 28 VME Arbiter and R uester 271 Pinout of the U2704 PAL is U2704 Pinout b sbr b sas gnd 1 p a 1 1 6 r 6 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 vee Is4sel ne loe Rev 1 oflOMay 1987 C01 TIDE TIAL ...

Page 256: ...asserted when P1_BR3 comes in from an external V ME device through U2401 NAND gate indicating that it wants the bus P1_BR2 Pl_BR1 and P1_BRO are monitored for the case where the 2060 board is a requester only When B_SSEL is asserted there are three possible state transitions depending on the state of B_SBBIN synchronized bus busy in indicating that an external dev ice is asserting Pl_BBSY on the V...

Page 257: ...is necessary in case there is another Release On Request VMEbus requester out there because such a device will not release PI_BBSY until it sees a request from another device The equation for the BUSREQ state is In state IDLE if B SSEL B SBBIN then state BUSREQ There are two possible transitions from the BUSREQ state once B_SBBIN has been negated depending on the state ofB_SAS at that point 1 IfB_...

Page 258: ...the VME address strobe Transitions from MASTER State The MASTER state is the nonnal condition of a release on request requester and the only time we leave this state is when an external device has requested control of the VMEbus When an external bus request is received pl_BR3 assened we need to look at several conditions 1 We will stay in MASTER state if P_RMC is assened which allows imple mentati...

Page 259: ...w pass filter on PI_BBSY on each 2060 board and because we don t know how many 2060 boards might be plugger into the backplane The equation for the MASTER_NG2 state is In state MASTER if B_SSEL B SBR P_RMC S4SEL then state MASTER NG2 When B_SBBIN has gone away we jump to BUSGRANT state where B_BGOUT is asserted to indicate that the external device requesting the VMEbus has been granted control o I...

Page 260: ...s overlaps the end of the CPU cycle with the time required by the bus grant signal to propagate down the bus grant daisy chain When several boards are installed this can be a significant amount of time on the order of 90 ns per board This overlap is allowed by the VMEbus specification because the next device must wait until PI_AS is negated before taking control of the bus If B_SSEL is not assened...

Page 261: ...titled VME Arbiter Requester Requester Only Mode which is in Appendix A The requester state machine starts off in the IDLE state waiting for either a B_SSEL signal from the CPU indicating a request for control of the V1dEbus or a PI_BG3IN signal from the arbiter indicating the V1vffibus has been granted to someone The equation for the IDLE state is In state IDLE B SSEL Pl BG3IN then state IDLE The...

Page 262: ...us B_SSEL assened the VMEbus is idle pI_AS and PI_BBSY negated and a bus grant has been issued pI_BG3IN asserted This happens when the CPU asserts B_SSEL just as a bus grant is being given to another device so we in effect intercept the bus grant intended for the other device The equation for the MASTER state is In state IDLE if B SSEL B_BG3IN B SBBIN B SAS then state MASTER Two transitions out of...

Page 263: ...It is in this state that the CPU perfonns its transfers to and from the V MEbus We leave the MASTER state when we see another device requesting the V1vIEbus via PI_BRa 1 2 or 3 the OR combination of which is called B_SBR U2401 as long as P_RM C or S4SEL are not asserted Just as in the Arbiter Requester case above P_RMC holds the VMEbus throughout a CPU read modify write cycle and S4SEL holds the V...

Page 264: ...negated before PI_BG3IN assened we jump to the IDLE state then to the BUSGRANT state when B_BG3IN is received The equation for the IDLE state is In state MASTER_NG if B SSEL B BG3IN then state IDLE 2 If we receive the bus grant at the same time that the CPU finishes using the VMEbus we jump directly to the BUSGRANT state The equation for the BUSGRANT state is In state MASTER_NG if B_SSEL B_BG3IN t...

Page 265: ...BG3IN If at that point B_SSEL is not asserted we jump back to the IDLE state whereas if it is asserted we jump to the BUSREQ state The equation for the IDLE state is In state BUSGRANTi if B SSEL B BG3IN then state c IDLE The equation for the BUSREQ state is In state BUSGRANTi if B SSEL B BG3IN then state BUSREQ sun Rev 1 ofl0May 1987 COI rIDEl 1 AL Il ...

Page 266: ...38 Memory RAM Pages 32 and 33 Memory RAM Pages 32 and 33 359 38 1 Memory Read 359 38 2 1emory Write 359 38 3 Processor Data Acquisition 359 ...

Page 267: ...mory RAM within the selected bank is coupled to the P2 data bus When m_rw is low a write cycle and output is enabled through the asser tion of the memory buffer enable signal m_ben a bit of data is written into each memory RAM within the selected bank from the P2 data bus Thus the truth table for the memory data buffers is Memory Data Buffers Data Flow Gate Direction Which way the m ben m rw data ...

Page 268: ...ect and Freeze State Diagram 288 NOI111a Operation 288 Deadlock Resolution 289 Vl 1E Short Timeouts 290 Vl 1E Long Timeouts 290 29 3 Vl 1E Master Controller PAL U2806 291 Tenninology for VME Master Controller 293 Vl 1E Master Controller State Machine 293 CPU Retains Control of V1 1Ebus at End of Cycle 294 CPU Relinquishes Control of V1 1Ebus at End of Cycle 295 CPU Freeze Cycles 295 Address Modifi...

Page 269: ...EL and controls the operation of the VMEbus Master Interface during VME rerun cycles A CPU rerun occurs under two sets of circumstances 1 when a VIviE device fails to respond within 2 88 microseconds or 2 when the CPU attempts to access the VMEbus at the same time as an exter nal VIviE master accesses the 2060 285 Rev 1 of 10 May 1987 CO FIDE llAL ...

Page 270: ...ONFIDE IIAL nout for the U2701 PAL Figure 29 1 Pinout of the U2701 PAL is U2701 PinouJ b torrn b tolat qnd 1 p a 1 20 1 6 r 4 2 19 3 18 4 17 _ 5 J 6 15 7 14 8 13 9 12 10 11 vee ne b es b ento Iso1se init loe Rev 1 ofl0May 1987 COl TIDEl lIAL ...

Page 271: ... active at state 5 o B_TOLAT VME TimeOut LATch Comes from the VME Rerun Timer U2700 and signifies that it s time to close the latches that allow VME DTACKs onto the 2060 board o B_TORRN VME TimeOut ReRuN Comes from the VME Rerun Timer U2700 and signifies that it s time to rerun the CPU because a V11E Slave has taken too long to respond This signal has meaning only when asserted in conjunction with...

Page 272: ...CPU will grant local bus access to a DVMA device and a DVMA cycle will be perfonned before the CPU begins the instruction again This would be the case if an Ethernet request E_DMAREQ and S_EHOLD or a refresh request R_DMAREQ were pending The second type of CPU rerun is called a deadlock Arbitration of deadlocks is required because the VMEbus makes no provision for backing off or rerunning a cycle ...

Page 273: ... A deadlock occurs when the CPU accesses the VMEbus just as an external VrvIE device that already has control of the VMEbus accesses the P2 bus As in nor mal operation above U2701 will proceed from state A to state B Then S_XREQ will be received either before or after the transition to state C 1 If S_XREQ is received during state B the state machine goes directly to state E 2 If S_XREQ is not rece...

Page 274: ...the rerun request by negating P2_AS at which point it will jump to state K by negating B_RERUN On the next clock the state machine will proceed to state L with the assertion of B_ENTO to start the VME short timeout counter counting the period until the next rerun cycle We will remain in state L until the state 4 of the next non DMA cycle indicated by S_DMA being negated and CS4 being asserted This...

Page 275: ...ing that into the count enable input of the VME Rerun Timeout Counter The VME Master Controller PAL controls VME address strobe data strobe transfer size output enable acknowledge enable and some address modifiers during VME Master cycles It is an asynchronous state machine that will run as fast as the PAL is able The PAL has one fairly complex state machine to handle output enable address strobe ...

Page 276: ...L is Figure 29 2 U2806 Pinout p1_dtaek 1 P a 1 24 ltlt 2 0 1 8 b ssoe 2 23 It b freeze 3lt 22 It p2_typ O 4 21 1r mb16sel 5 20 It lt q_top6 k 6 19 p2_a OOj 7 18 p2_a 01 8 17 b aen 9 16 b ssel 10 15 p2_siztO 11 14 gnd 12 13 vee b aeken b_uds Rev 1 of 10 May 1987 CONFIDEI i AL ...

Page 277: ...ction this signal is active when P2_A 31 24 are all high This function is shared with the Video section to save an IC and chooses between 32 and 24 bit VME addressing modes on Master cycles o MMU_TYP O The low order type bit generated by the MMU It is used here to distinguish between 16 and 32 bit VME accesses When MMU_TYP l is high MMU_TYP O low indicates 16 bit VME data space and high indicates ...

Page 278: ... byte size M P2_AOO II P2_SIZ O P2_SIZ I not word aligned P P2_AOO When the VME Slave currently being addressed responds with a Pl_DTACK or Pl_BERR this will be sent to the CPU which will negate P2_AS lfno other VME device has requested control of the VMEbus the 2060 board will retain control by continuing to assen PI_BBSY and will indicate this to the VME Mas ter Controller PAL by keeping B_AEN a...

Page 279: ... VME data strobes and clears out the acknowledges as it moves from states F M or P to state H then disables the drivers by negat ing B_OECPU as it moves from state H to state J Now that the drivers are dis abled we can remove the VME address strobe which takes us to state K States K and L don t perform any tasks When the VME Master Controller is waiting in states F M or P and B_FREEZE is asserted ...

Page 280: ...own in the figure titled Sun 3 Physical Address Mapping which is in Appendix A The 68020 allows several types of transfers that are not allowed by the VMEbus Specification including non word aligned word accesses non Iongword aligned longword accesses and three byte transfers o A non word aligned word transfer will result in a byte being read or written o A longword transfer to an address misalign...

Page 281: ...ve Address Decoder U2907 299 Tenninology for the V v1E Slave Address Decoder U2907 301 30 3 User DVMA Enable U2905 6 and Context Registers U509 302 30 4 V v1E Slave Address Multiplexers U2910 09 302 30 5 V11E Slave Request PAL U2904 302 Tenninology for V Slave Request PAL 305 V v1E Slave Request State Machine 306 ...

Page 282: ...r Address bits PI_A l9 04 are latched in O type flip flops ALS374s U2913 12 also on the leading edge of PI_AS They are enabled onto the processor address bus when the OVMA Controller grants control of the P2 bus to the V ME Slave interface X_OMAEN is true Address bits PI_A 03 01 and Pl WRITE are latched into U2911 on the rising edge of PI_OS ALS technology was chosen here to minimize undershoot on...

Page 283: ... PAL is Figure 30 1 U2907 Pinout b_a 20 1 p a 1 20 vee 1 6 1 8 b a 21 2 19 b sdr a b a 22 3 18 b am5in 11 b a 23 4 17 b am4in 11 b a 24 5 lE b iaci b_a 25 6 15 b a 3Q b a 26 7 14 b_a 31 b_a 27 8 13 b aen b_a 28 9 12 b_uspe gnd 10 11 b_a 29 Rev 1 of 10 May 1987 CO TIDENTIAL ...

Page 284: ... 24 bit address space system DVMA o B_USPC stands for VME User Space and is roughly analogous to the User fonn ofB_SDMA except that it goes through a further level of qualification before becoming a valid decode at which point it is called B_UDMA B_USPC goes active if the address bits indicate an access to the top 2 giga bytes of the 32 bit VME address space if vcc b_uspc b_a 31J b_am5in b_am4in b...

Page 285: ...ssening B_USPC as explained above then output B_UDMA will be asserted The V v1E Slave Address Multiplexers are two 4 bit tri stable multiplexers that drive processor address lines P_A 27 20 during VME Slave cycles On User DVMA cycles they choose the latched VME address lines B_A 27 20 On Sys tem DVMA cycles they drive P_A 27 20 to all ones causing the System DVMA to be relocated to a virtual addre...

Page 286: ...the next cycle not to begin until DTACK from the previous cycle goes away The synchronous implementation locked out the next cycle for approximately 100 nanoseconds while the synchro nous implementation locks it out for only about 15 nanoseconds Rev 1 of 10 May 1987 COJ FIDE TlAL ...

Page 287: ...igure 30 2 U2904 Pinout Ie 60 1 p a 1 20 vee 1 6 r 4 s aek 2 19 en sav r a Ip1_s1ds 3 18 Ip2_as l _ 1 1 Ip1_suds 4 17 Is x eq p1_sas 5 16 Ib d c 5 error 6 15 Ib errou Ib sdrna 7 14 Ixgran Ix dmaen 8 13 len bex Ib udrna 9 12 Ib endo gnd 10 11 loe 1 Rev 1 of 10 May 1987 CO TIDE JIAL ...

Page 288: ...s J EN_SDVMA ENable System DVMA Comes from the System Enable Register U1406 and indicates that DVMA from the VMEbus has been enabled for System Mode User Mode is enabled by the User DVMA Enable Register U2905 J PI_DS VME Data Strobe Not actually a signal on the VMEbus this sig nal is active when either or both PI_DSO or PI_DS1 are active It exists to minimize inputs to PALs that require only the p...

Page 289: ...tion with the synchronized VlviE address strobe PI_SAS and at least one V1v1E Data Strobe PI_DS The equation for the IDLE state is In state IDLE if Pl SAS Pl DS B DTOUT B ERROUT then state IDLE The equation for state A is In state IDLE if Pl SAS Pl DS B DTOUT ADDRESS_DECODE B_ERROUT then state A This address decode can be either of B_SDMA or B_UDMA indicating an access to the system address space ...

Page 290: ...nal a tennination with error The equation for the state E is In state Di if B SXDMA X DMAEN S_ERROR then state E Either state D or E will signal to the external master to end its cycle which will cause it to respond by negating the VME data strobes We will see this as a negation of PI_DS state D When this happens we will jump back to the IDLE state The equation for the IDLE state is In state D or ...

Page 291: ... also wait for B_SXDMA to go away we are guaranteed enough time to decode the new address before we reassert XREQ It is important to remember that worst case the clock on the 2060 board is 90 nanoseconds long and so it is conceivable that an external master could be fast enough to do this Rev 1 of 10 May 1987 COSFIDEl TIAL ...

Page 292: ...31 VME Data Buffers U3000 to U3006 VME Data Buffers U3000 to U3006 311 31 1 16 BitOperation 311 31 2 32 Bit Operation 312 31 3 CPU Cycles 312 31 4 DVMA Cycles 312 ...

Page 293: ...igure labelled Carrera VME Diagnostic PROMs Data Paths in Appen dix A sections A F show the different operating modes used in TYPE2 space the VtvfE 16 bit data space D When the CPU writes or reads the top half of the CPU data bus is connected to the bottom half of the VME data bus sections A and B of the diagram via the cross buffers D When an external VME master writes to the P2 bus the bottom ha...

Page 294: ...n signals to be illegally active at the same time On writes the enables are also held during Freeze cycles See the section on the VME Select and Freeze PAL for more information on Freeze cycles On writes the transparent latches open at the beginning of the cycle and remain open for the duration of the cycle On reads the latches open at state 6 and like wise remain open for the entire cycle The ena...

Page 295: ...l Memory Access 315 32 1 A Generic DVMA Cycle 315 32 2 Optimizations to the DVMA Cycle 316 Back to Back DVMA 316 Ethernet Hold 316 V1 IEbus Lock 316 32 3 Refresh as a Special Case 316 32 4 The DVMA Strobe PAL U241 0 317 Input and Output Signals 319 ...

Page 296: ...A devices and o handles assertion and negation of the address strobe on DVMA cycles Requests can be generated by the Refresh subsystem the Ethernet Controller and the VME Slave Interface and are prioritized in that order which is to say that if two requests are pending at the point when the DVMA Controller gets the bus from the CPU the one with higher priority gets serviced first The DVMA Controll...

Page 297: ...tween the CPU and the DVMA Controller which amounts to four clocks for each round trip Secondly it is possible for devices to keep control of the P2 bus even when they aren t using it The Ethernet interface can assert S_EHOLD to retain control of the bus While S_EHOLD is asserted the DVMA Controller will continue to assert P_BACK keeping the CPU off the P2 bus Refresh cycles will still get access ...

Page 298: ...a refresh cycle By that we mean that the bus is always given back to the CPU after a refresh cycle as a sort of fail safe feature in case one of those subsystems breaks down If this hap pens the CPU will still be able to limp along albeit extremely slowly The DVMA Strobe PAL generates the P2 bus control signals with the exception of address strobe which is generated by the DVMA Controller that are...

Page 299: ...318 2060 CPU Board Engineering Manual CO FIDE lIAL Pinout of the U2410 PAL is Figure 32 1 U2410 Pinout ft 1 2 p a 1 20 1 6 1 8 19 ft gnd s d T a Rev 1 of 10 May 1987 CO FIDE TIAL ...

Page 300: ...d during external DVMA cycles that are occurring in the system DVMA part of the address space as defined in the Sun 3 architecture manual d pub used only during board test to check the operation of the p_fcO output Outputs from the U2410 PAL are p fcO p_fcl p_fc2 processor function codes used by the 68000 family to generate 8 separate address spaces processor size codes used by the 68020 for dynam...

Page 301: ...ord 1 1 3 byte 0 0 longword Table 32 2 MC68020 Function Code Output Encodings pJc2 pJcl pJcO cycle type 0 0 0 undefined reserved 0 0 1 user data space 0 1 0 user program space 0 1 1 undefined 1 0 0 undefined reserved 1 0 1 supervisor data space 1 1 0 supervisor program space 1 1 1 cpu space Rev 1 of 10 May 1987 C01 TIDEl TIAL ...

Page 302: ...bus Currently Bus Master 325 CPU Rerun During V1ffi Access 325 Relinquishing the V1vfEbus 326 33 2 Vlvffi Slave Cycles 327 V1v1E Device Accesses P2 Bus 327 Lock Mode Cycles 328 V1v1E Device Initiates P2 Bus Lock 328 VME Device Ends P2 Bus Lock 329 V1v1E Device Not Fast Enough to Initiate P2 Bus Lock 329 33 3 Ethernet Cycles 329 33 4 Refresh Cycles 330 ...

Page 303: ...ing P2_AS at state 1 2 By state 4 the MMU has finished its address translation and indicates that this is a V1 1E Master cycle by asserting MMU_VME 3 M 1U_VME goes into the VME Select and Freeze PAL U2701 causing it to assert B_SSEL at state 5 4 B_SSEL goes into the VME ArbiterlRequester PAL U2704 which observes that the VMEbus is idle by checking that P1_BBSY and PI_AS are inactive 5 On the next ...

Page 304: ...next falling edge and on the following falling edge negates P2_AS 14 Negation of P2_AS causes the V ME Master Controller PAL U2806 to immediately negate the V ME address and data strobes and clear B_DTACK from flip flop U2804 by negating B_ACKEN 15 The V ME slave responds by negating PI_DTACK at some arbitrary time in the future 16 At state 1 of the next cycle B_SSEL will go away and the cycle wil...

Page 305: ...ve currently being addressed has a response time of greater than 2 88 microseconds or when it takes the CPU a while to gain control of the VMEbus the CPU will be instructed to rerun its cycle This will cause it to re arbitrate for the P2 bus and allow other pending DVMA cycles to complete before it re attempts the cycle This situation is shown in the figure labelled CPU Rerun During V1vffi Access ...

Page 306: ...ifferent way as shown in the timing diagram labelled CPU Relinquishes VMEbus Currently Bus Mas ter in Appendix A release Pl_BBSY as soon as we detect both PI_BR3 and PI_AS so that the VMEbus grant will be able to make its way down the daisy chain while the last cycle is in progress overlapping the two processes The cycle goes like this 1 In the timing diagram we see the external device assert PI_B...

Page 307: ...o the bus grant by asserting Pl_BBSY indi cating that is has taken control of the VMEbus 5 This is received by the VME Arbiter Requester as B_SBBIN causing it to release the bus grant signal 6 After the external master takes control of the VMEbus it will enable its addresses and data onto the VMEbus and assert its address and data strobes PI_AS and Pl_DS l O 7 The addresses will be latched in the ...

Page 308: ...state 9 instead of state 7 for two reasons to satisfy the VME data to DTACK setup time and to allow time for parity checking The VMEbus doesn t allow simultaneous assertion of DTACK and BERR so the data must be checked before asserting DTACK 23 The external master will respond to Pl_DTACK by negating its VME address and data strobes 24 This will cause Pl_DS to go away 25 When Pl_DS is deassened th...

Page 309: ...CK will be negated and control of the P2 bus will be returned to the CPU This situation is shown in the timing digram labelled VME Device Ends P2 Bus Lock in Appendix A where we see the last V11E Slave cycle A certain amount of time is wasted at the end of Lock Mode because the DVMA controller holds onto the P2 bus for approximately six cloch before deciding that it is no longer required If the ex...

Page 310: ...e required in order to keep from having contention on these lines On reads signal E_RDTI indicates the TI period in Intel parlance On the next ris ing edge ofE_C125 one ofE_RDU or E_RDL goes active depending on which half of the P2 bus is being accessed These signals enable the Ethernet Data Buffers U2508 11 onto the local Ethernet address data bus at a time guaranteed to be after the 82586 stops ...

Page 311: ...ed in U704 6 RAS PALs U3100 and U3102 assert RAS to all banks of RAM simultane ously 7 REFR is delayed by two flip flops to form R_SAS and R_SSAS 8 R_SAS causes the DVMA controller to release P_BACK so that the CPU can start the process of retaking the P2 bus 9 R_SSAS ends the cycle by telling the DVMA Controller to negate REFR and R_DMAEN Rev 1 of 10 May 1987 CONFIDENTIAL ...

Page 312: ...e PALs U3100 and U3102 RAS Decode PALs U3100 and U3102 335 34 1 U3100 and U3102 Pinouts 335 34 2 U3100 and U3102 Input Signals 336 34 3 U3100 and U3102 Outputs 336 U3100 Output Signals 337 U3102 Output Signals 339 ...

Page 313: ...connected to the two odd megabytes in the four megabyte space megabytes 1 and 3 The rasE signals go to the two even megabytes 0 and 2 In other words CJ RAS to megab 1e 0 comes from U3100 CJ RAS to megabyte 1 comes from U3100 CJ RAS to megab 1e 2 comes from U3102 CJ RAS to megabyte 3 comes from U3102 U3l00 and U3l02 Pinouts p2 uas 1 p a 2C vee p2_endras 2 19 rasO CS p2_devsp 3 18 a sE 2 p2_re r 4 1...

Page 314: ...dress from HMU to select 1 of 4 Megs p2_a 01 00 physical address from bus master to select bytes 34 3 U3100 and U3102 Outputs from U3100 and U3102 are Outputs U3100 03102 rasE_24 Meg 0 Meg 2 byte 24 rasE 16 Meg 0 Meg 2 byte 16 rasE 08 Meg 0 Meg 2 byte 08 rasE 00 Meg 0 Meg 2 byte 00 rasO 24 Meg 1 Meg 3 byte 24 rasO 16 Meg 1 Meg 3 byte 16 rasO 08 Meg 1 Meg 3 byte 08 rasO 00 Meg 1 Meg 3 byte 00 Deriv...

Page 315: ..._all p2_al2 p2_all first megabyte second megabyte third megabyte fourth megabyte U3100 Output Signals Now we can list the PAL equations for the eight RAS signals issued from U31 00 and the eight RAS signals from U3102 Remember that o U3100 issues RAS to megabytes 0 and 1 o U3102 issues RAS to megabytes 2 and 3 The following eight signals are issued from U31 00 The RAS strobe for upper data byte da...

Page 316: ...refr RAS always on refresh The remaining RAS signals are decoded similarly RAS to byte 15 08 in mega byte 0 is rasE 08 DORAS MEGO p2_al p2_aO DORAS MEGO p2_sizl p2_sizO p2_al DORAS MEGO p2_sizl p2_sizO p2_al DORAS MEGO p2_sizl p2_al p2_aO p2_refr RAS to byte 07 00 in megabyte 0 is decoded rasE 00 DORAS MEGO p2_al p2_aO DORAS MEGO p2_sizl p2_sizO DORAS MEGO p2_sizl p2_al DORAS MEGO p2_sizl p2_sizO ...

Page 317: ...MEG1 p2_siz1 p2_a1 p2_aO p2_refr RAS to byte 07 00 in megabyte 1 is decoded rasO 00 DORAS MEG1 p2_a1 p2_aO DORAS MEG1 p2_siz1 p2_sizO DORAS MEG1 p2_sizl p2_a1 DORAS MEG1 p2_siz1 p2_sizO p2_aO p2_refr U3102 Output Signals The following eight signals are issued from U3102 PAL Remember that DORAS and MEG 3 0 are macros defined as define MEGO define MEG1 define MEG2 define MEG3 p2_a12 p2_a11 p2_a12 p2...

Page 318: ... to byte 15 08 in megabyte 2 is decoded rasE 08 01 DORAS MEG2 p2_al p2_aO DORAS MEG2 p2_sizl p2_sizO p2_al DORAS MEG2 p2_sizl p2_sizO p2_al DORAS MEG2 p2_sizl p2_al p2_aO p2_refr RAS to byte 07 00 in megabyte 2 is decoded rasE 00 DORAS MEG2 p2_81 p2_80 DORAS MEG2 p2_sizl p2_sizO DORAS MEG2 p2_sizl p2_81 DORAS MEG2 p2_sizl p2_sizO p2_aO p2_refr RAS to byte 31 24 in megabyte 3 is decoded DORAS MEG3 ...

Page 319: ...refr RAS to byte 15 08 in megabyte 3 is decoded DORAS MEG3 p2_al p2_aO DORAS MEG3 p2_siz1 p2_sizO p2_al DORAS MEG3 p2_sizl p2_sizO p2_al DORAS MEG3 p2_sizl p2_al p2_aO p2_refr RAS to byte 07 00 in megab 1e 3 is decoded rasO 00 DORAS MEG3 p2_al p2_aO DORAS MEG3 p2_sizl p2_sizO DORAS MEG3 p2_sizl p2_al DORAS MEG3 p2_sizl p2_sizO p2_aO p2_refr Rev 1 of 10 May 1987 CONFIDE TIAL ...

Page 320: ...35 CAS Decode PAL U3104 CAS Decode PAL U3104 345 35 1 U3104 Pinout 345 35 2 U3104 Input Signals 346 35 3 U3104 Output Signals 346 ...

Page 321: ...of its output signals x_we and x_cas are buffered by U3105 and U3115 control buffers o x_we is used to generate write enables for the eight banks of memory o x_cas generates the column address strobes for these same eight banks of memory Pinout for U3104 CAS decoder PAL is U3104 Pinout p2 bot32M 5 6 gnd 10 pal 20 vee 18 n 8 14 m_parrd 13 m rw 11 test 345 Rev 1 of 10 May 1987 COSFIDESTIAU ...

Page 322: ...lects bottom 32 Mbytes select 2 or 4 Mbytes in a 32 Mbyte address range only used when applying test vectors used to break loops 35 3 U3104 Output Signals Outputs from the CAS deCoder PAL are x we x cas m rw m ben modified version of R W signal generates write enables for all memory CAS for all memory gate parity read data to p 2 par 24 16 08 OO read write control for the memory data buffers ackno...

Page 323: ...lse define MEG4 i endif p2_a24 p2_a23 p2_a22 p2_a21 2 Mbyre system p2_a24 p2_a23 p2_a22 4 Mbyte system Finally memory on the CPU board is defined as occupying a portion of the bottom 32 Mbytes of address space M_SEL or memory select defines this space Write enables are generated by a slightly modified version of the R W sig nal and must not change until CAS has been deasserted Otherwise reads may ...

Page 324: ... data to p2 par 24 16 08 00 when selected and doing a read J arrd x ca READ p2_ua The p2_TW signal is passed straight through Generate p2_ack as soon as the board is selected By A 1 ing with p2_uas we drive m_ack high before shuning off since p2_uas is deassened before p2_cas or m_sel Tum on the P2 data buffers when selected doing either a read or a write p2 uas WRITE Rev 1 of 10 May 1987 COSFIDE ...

Page 325: ... 36 Control Buffers U3105 and U3115 Control Buffers U3105 and U3115 351 ...

Page 326: ...ard memory U3105 drives four of the eight write enable and four of the eight CAS signals to on board RAM U3115 drives the otheF four write enables and CAS signals to on board RAM These buffer drivers are permanently gated ON by the connection of pulldo I1s to both output enables 351 Rev 1 of 10 May 1987 CONFIDE1 TIAL ...

Page 327: ... J 37 Rowand Column Address Multiplexers U3110 07 Rowand Column Address Multiplexers U3110 07 355 ...

Page 328: ...ress bits access a word plus 2 bits of parity from the entire 2 4 Mbyte memory space which is why the LSB of the RAS CAS decode is p2_a 02 Figure 37 1 RASICAS Decode Bit Assignmentsfor 2 and 4 Mbyte Systems 2 Mbyte Decode number ofbilS 11 9 4 Mbyte Decode 9 2 During the assertion of p2_mux aliased cs3 the row address bits p2a 09 02 are gated onto the m_a 7 0 memory address bus The ninth bit p2_a 1...

Page 329: ...bus The ninth address bit is supplied through U3109 mux and U3110 buffer CAS is now valid and is assened to the memory RAM Both row and column address bits are latched into row and column decoder registers inside each RAM chip with the assertion of their respective RAS and CAS signals J3101 selects p2_a12 for a 2 Mbyte system or p2_a21 for a 4 Mbyte system Rev 1 of 10 May 1987 CO FIDE JIAL ...

Page 330: ...A Figures and Timing Diagrams Figures and Timing Diagrams 363 ...

Page 331: ... A Figures and Timing Diagrams 363 Rev 1 of 10 May 1987 COr FIDE JlAL ...

Page 332: ...resses 4 CPU Access of Idle VMEbus state diagram 323 CPU space 24 CPU Space PALs U106 and UI07 24 ctlspc signal 28 365 D data alignment 61 device space 24 devspc signal 28 DVMA 315 Optimizations to the DVMA Cycle 316 Refresh as a Special Case 316 Sample Cycles 323 U2407 315 U2408 315 U2409 315 U2409 DVMA Controller 315 U2410 315 U2410 DVMA Strobe PAL 317 DVMA Direct Virtual Memory Access 315 dynam...

Page 333: ...d Buffer 184 U904 MOS ReadIWrite Strobe Decoder 179 User accessible EAROM EEPROM 165 MOS Read and Write Cycles 185 366 o Offset Bits 60 Optimizations to the DVMA Cycle 316 Back to Back DVMA 316 Ethernet Hold 316 overview of Sun 3 architecture 3 68881 3 control space devi s 4 CPU 3 DVMA controller 4 EEPROM 5 Encryption processor 5 EPROM 5 FPA 3 00 devices 5 interrupts 6 main memory 5 Memory Managem...

Page 334: ...id signal 221 rd_int signal 208 rd_keybdm signal 182 rd_padOO signal 210 rd pad08 signal 209 367 PAL equation continued rd pad16 signal 209 rd pad24 signal 157 rd par signal 208 rd_serial 182 rd_5Ysen signal 222 rd_tod signal 183 rd_usreIl signal 222 rdcnO signal 238 rden1 signal 239 renm signal 33 I_mor signal 155 samp1e signal 160 ti_d 3 0 signals 117 lIack 197 ttlbfen signal 196 vcopydet signal...

Page 335: ...06 24 input signals 26 output signals 27 pinout 26 U107 24 30 input signals 31 output signals 31 pinout 30 U11oo 187 U1100 Serial Ports Receive Dat 1 Path 188 Transmit Data Path 188 368 U1400 TIL Bus Sack State Machine 195 cycle timing 203 outputs 196 pinout 195 read cycle 203 state diagram 198 write cycle 203 U1401 TIL Bus Device Decoder 204 inputs 205 outputs 206 pinout 205 U1402 MMU Decoder 210...

Page 336: ...errupt circuitry 67 U301 0 Interrupt Enable Registers 68 U302 Lower Priority Encoder 78 369 Index COnlinued U302 Lower Priority Encoder continued input signals 79 output signals 80 pinout 79 U302 U304 InternIpt circuitry 73 U303 Higher Priority Encoder 84 inplt signals 84 output signals 85 pinout 84 U304 Second Level Interrupt Priority Encoder 89 input signals 90 output signals 90 pimut 89 U305 94...

Page 337: ...te Machine 257 U1500 Buffer 253 U1501 Byte Decode PAL 250 U1502 Video Control Decoder 236 U1503 P2 Interface State Machine 241 I 1504 Video Select Decoder 234 VIS05 DIP 253 VI605 Q7 241 370 Video Circuitrv cOnJirwed U1607 233 U17OO 01 Video RAS CAS Latches 254 VARB and Video Side State Machines 242 Vertical State Machine 257 Video Cycle Timing 233 Video Read 243 Video Write 247 Video Write Timing ...

Page 338: ...oint Processor The FPP can be run on an independent clock All CPU space cycles vill be implemented as in 3 1 Disabled System Enable register 06 0 FPP coprocessor cycles vill be terminated vith an immediate bus error All other coprocessor addresses and accesses to an enabled but uninstalled FPP vill result in a Timeout bus error Interrupt Acknovledge cycles and installed and enabled FPP cycles vill...

Page 339: ...r register hich is byte read only The IO PROM Page Map and tbe Segment Map are implemented as an array of bytes This viII allo vord and Icn Jord accesses via the 68020 dynamic bus sizing capability ADDRESS OxOOOOOOOO Virtual Ox10000000 Virtual Ox20000000 Virtual Ox30000000 Ox40000000 Ox50000000 Ox60000000 Ox70000000 Ox80000000 to OxEOOOOOOO OxFOOOOOOO 2 2 2 Hemory Management Unit DEVICE ID PROM Pa...

Page 340: ...l rate viII be 10 nsec per pixel The outputs to the video monitor vill be as follo s 1 Serial Video differential ECL 2 Horizontal Sync positive TTL pulse sync on rising edge 3 Vertical Sync positive TTL pUlse sync on rising edge 2 3 3 I O Devices TYPE1 space The folloving devices viII be implemented in TYPE1 21 bit address 4 space as per the Sun 3 Architecture Hanual 5 2 6 4 to 6 fII ADDRESS OxOOO...

Page 341: ...he VHE address size TYPE2 32 bit Address OxOOOOOOOO OxFFOOOOOO OxFFFFOOOO TYPE3 32 bit Address OxOOOOOOOO OxFFOOOOOO OxFFFFOOOO 2 4 Interrupts VHE bus vith lS bit data VKE 32 bit address space VKE 24 bit address space VHE 16 bit address space VHE bus vith 32 bit data VME 32 bit address space VHE 24 bit address space VKE lS bit address space AM5 3 H Address Modif1ers L L H H H H H L H I O access on...

Page 342: ...other DVHA devices Refresh Ethernet can obtain the local bus After 128 retries a timeout error will occur This will provide a timeout when the CPU board is master No timeout will be provided for VHE Slave or User mode since it is the responsibility of each master to provide it s o n timeout 5 Backotf Mechanism If the CPU starts an access to the VME at the same time a VME devices accesses the P2 th...

Page 343: ...ection 2 3 This Device Space is divided into four types typeO for main and video memory type1 for I O and Control devices and type2 3 tor the VME Master interface 4 2 Data paths Figure 2 provides details about data bus connections There are tvo bus sizes a 32 bit and an 8 bit The 32 bit bus provides a high bandvidth path betveen the CPU and DVMA devices and main memory An 8 bi bus size is used to ...

Page 344: ...rs The other five connectors are the 9 pin Video output 16 pin Ethernet two 26 pin serial ports and a 16 pin long distance keyboard and mouse connector Tbe bas1c Expans10n board has the three P1 3 VME bus connectors Additional connectors will depend on what other functions besides memory il1 be on the board 6 3 Switches There are two user accessible switches One is the diagnostic switch which is u...

Page 345: ...ihJIJ p IIIJIJ D e lrol Ul 1 Y J Ie 1 __ 11 eon 1 01 I b 1 b bbout U t UME bller h _ bu reque te conlrol Ie dtol n 1 I I rea 1 1 conlrDI d q ut 0_ 1 01 0 JtI1 I 1 _ con Iroller J I IU1J llJ Inl r lte 0 111131 I pl d l l9IJIJ pl nIl31 J 1 ...

Page 346: ... _ f L 1 I f lj UIIl n 1110 ro _ 1 POGE MAPS G_ _ m s CHTXT RfG PC 131 J O V I en Spnr o r t I t I r I 1 f u fJ f r l l n J pnR R I r l H R 1 t r n ERROR LnlCH HE prG ousr REG COIHROI 8 IO 1 I Con Irol SpArR __ _ _ _ _ 2050 DATA BUSSING JOE MURPH REU 1 ...

Page 347: ... 1 r if _ _ _ 11 r Q I _ l I OL io _ OL_ _ Ale_ La aJa l tl _ _ _I to _ L _ 0 _ u _ 1 _ _ OL to lNL _ _ rn i It aJ IP I I I I r f b2J I Id f _t IL 1 OL _ rtF _ __ 111 II __J _ _a tooL 1 8 r ___ L _ f I _1 _ I 11 J l ...

Page 348: ...utput of the bus mas ter 66020 or VME For p2_a 31 13 timing is rrunu a f244 where mmu_a 100 Vlorst case p_a seLram page_ram For p2_a 12 00 timing is p_a f244 Bidirectional data bus For processor writes is p_dw als245 Writes to memory are early writes Buffered version of the bus master s size bits They are used in tandem with p2_a Ol 00 to determine which bytes need to be selected for a given cycle...

Page 349: ...is signal is asserted on s2 f74 and deasserted on cycle f74 Equivalent to CS2 Timing strobe to determine when to switch the address presented to the rams from row address to column address When low we are selecting the row address and when high the column address Is equivalent to CS3 Signal to qualify p2 cycles Indicates that the cycle is legitimate memory cycle because we doing a device space cyc...

Page 350: ...ike normal memory cycles Obtain the bus like a full blown bus master would do but then just gate the refresh address onto at least p2_a 11 02 10 bits assumes that the largest rams for product life time will be 1 Mbit and one clock later assert p2Jefr for 3 clocks Tras 120ns 2 clocks skew_slop T 1 fe 1 Qc c c J fC r c 1oc k P2 Bus Definition February 1 1985 3 ...

Page 351: ...51 5 2 53 S j SS E 57 5 51 o h f 2 h3 70 71 1 1 73 7 f 75 7G 77 7 DES K PT 10tJ itt LS fb3 3 2 S6 7L fAL537 f 1 At s 0 1 74 F5 7 7 1 F 3 2 12 71 fF373 7 f ALS 173 7L IALS2 5 7A 7 F 51 iLfFO 6 7ttr o9 7 1L57 13 7 1 F53l t f 11 1 7 A 7 fLS llA 10 HI 0 1C l Hr 2 Y 10 H 125 loH 131 0 H 3 IC I 2 L 5 29 z LS30 s o 1LfLSo f 7 FIS7 3312 PI DIP 5 3 33M t O c It 0 t 11 t oIIIiIrt I VII l l r r I B ATi LllH ...

Page 352: ...0 j loc f l J 00 e 0 S 2 J P 1 n 0 f p 1 1 ec l r III 8 pi h C1 a E II 1 0 0 P H d Di tie ItJ LII f 51 l k 2 71 2 3 7 r 70 0 5 70 K 12 5 70 1 1 5 7c 7 I 10k C i 5 J I t JL i 7 p Sorr IS f t I OOJ 00 a I f J c o l A l ce Nc 4 J I 7 I te _r f 0 ...

Page 353: ...oe 7 i F 5 4 25 7 F3 I f TI TI L I I I rc lo TI Fa rc 6 FOo rr h lJ f 1i rc A 4 _Ff4 i rc t i lJ TI II I t L T Tr _ TI F i rd i lei Fair 1 i _ T 1_ T F i r l1 Id il F dl F lr TI Il T1 1 t TI TI I Motoca I J V 1 Mo toro l S vo e t i cs S 51I t cr t of r e IC S iJ t Qt c S tJCl i lJ c o N G tJQ t O l t 1 1 _ S 3 e c M 1 r i Si3 l 5 j e __ L 5 IC J S 5 01 C 0 1 1 Il l I 5 3 1 7 t r i ...

Page 354: ... t 1A TI AMP AM AMi AnD Af1D n A 1D AMD AMi AI 1L MM 1t1 MMJ 1 1111 l1 ir 11M X S I e t c To I Fuj J 5 1 f f 55 _4Lf_ __ _ f J1 _________ l 1o to I r _ _ _ 71 7 l C _ _ _5 o I r i I 411 _ t 7 oH f3 _tlo I a _ t1r J l _ r l _ I _ l It __ _ 3 A _ __ _ IktC Ij Mt ic fj f1 I h __ J1t v ...

Page 355: ...2 1 1 FC3 1 1 FC4 illegal 1 1 FCS 1 1 FC6 1 1 FC7 1 DATA 1 2 of Device Space 1 1 PRGM 1 2 of Device Space 1 Byte decode strobes Leave as 30 Can be either p2_a or p_a as appropriate 1 define BYTE24 define BYTE16 define BYTE08 define BYTEOO lal aO 1301 300 301 300 301 aO 1 Map for Control Space elements 1 define IDPROM Ip_a31 p_a3o p_a29 p_a28 1 0 1 define PAGEMAP Ip_a31 p_a3o p_a29 p_a28 1 1 1 defi...

Page 356: ... apalr apal apal_ts_i apal_th_1 1 vme arb1ter define vme_arb_palr define vme_arb_pal_ts_i define vme_arb_pal_th_1 apalr apal_ts_i apal_th_1 1 1 16R4 1 1 vme master define vme_master_pal define vme_master_pal_stev apal apal_skev 1 1 20LS 1 1 vme slave space address decoder define vme_slvspc_pal apal l lSLa generator apa1r apal apal ts i apal th i vme slave request vme_s1vreCLpa1r vme_51 vreCLpal vm...

Page 357: ...pa1_ts_i bpal_ts_i define clock_pa1_th_i bpal_th_i 1 uP 1 define mmuval1d_pal bpal 1 mmu 1 define cpuspace_pal bpal 1 16rSb 1 1 16l8b 1 1 181Sb 1 1 mem I define ras_pa1 bpal I 1818b I define cas_pal bpa1 1 161Sb 1 define mem_pal apal 1 1618a 1 define mem_pal_on apa1_on define mem_pal_off apal_oft 1 io decoder I define iobus_pal pal define mosbus_pal pa120l10 1 20110 1 define ttlbus_pal pa120110 1 ...

Page 358: ... R V OF B NO SUN MICROS STEMS INC l nsuu _____________ L 0_nT_E l __ Ls c Al E P c_6B uL JlJlSLJ P_8S r_dmareq r_dmaen r_ssas ...

Page 359: ...f r L __I n IUL1i NJ UiJLJLJL o_c125 1 8_ho I d _ 8_readl l I p_back _ _ _ r 1 J 1 ...

Page 360: ... Cycle u I I 11 I I I I I I J I h I r1 f CPu_ I ri rf n I v h I ck h V i S h f I r rna I K N _ krq f SUN MICROSrSTEMS INC 8 HO REV DATE SCN E OF ...

Page 361: ...f pl_bbs lLr L l I CPU Cycle b_ sxd m a _ b_lock p_back _ p_br b_lockrq SUN MICROSYSTEMS INC UME_Devlce_No _Fas _Enough_to Inl ia e_P2_Bu5_Lock B NO REV DATE 1 SCALE PAGE ...

Page 362: ... 11 L F pl_bbs yl _ s_ack b_ 1sxd m a f l b_lock p_b ack p_br f b_lockr q pl_ud J IL J pl_5uq5 pt s105 111 0_____ b_endo J L r B SUN MICROSYSTEMS INC NO REV DATE l SCAlE PI Gf or ...

Page 363: ... SUN MICROSlSTEMS INC UME_DevicB_Acquires_UMEbus and_Accesses_P2_Bus 9 DI TE HO SCI Il E PAGE OF J fU ...

Page 364: ... RfU NO SUN MICRosrSTEMS INC _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ L _ _ _ __ S CAL E Pf r O_F_ _ _ _ b_uds 1 d s_ 4_ __ lf _f I c_60 LJLJU U U U U U l J U U k ex roal IlI9sler vkps Con tro ...

Page 365: ... _ 1 h un r su f u _ b_ Ids I ck k n ____I SUN MICROSYSTEMS INC CPU_Rerun_Durlng_UME_Access Currenlly_Bus_Ms5Ier b_ t orrn _ b_freeze NO SCALE PI JE OF REU ...

Page 366: ... mmu_vme Ui P l_bbs yL _ _ 4 _ b_sbb I n _ _ I f _ _ b_aen 1 1_ _ pl_dtack b_ssoe _ _1 b_oeq u _ f _ _ _ t SUN MICROSYSTEMS INC EV OF ...

Page 367: ... RfU OF PI GE NO SCI IlE SUN MICROSrSTEMS INC B DATE 1 1 1 _ _ c 60 II p2_as mmu_vme b_ssel pl_bbsq b_sbbln b_aen b_oacpu b ssoe b_as pl_uds pl pl_dtack b_dtack b_8cken b_brout pl_as b sas ___ ...

Page 368: ... _ _ _ _ _ _ pc_t Yr mmu_vme b UdS _ _b_ _ld_S_ L_t__ f pl_dtack 11 0 b_dlack SUN MICROSYSTEMS INC D I DAlE 1 1 ISCN E TPAGF OF ...

Page 369: ...3114 2060 s memory actnovledgl buffer control pal Ip2_rv 1 pal 20 vcc 1 8 1 8 Ip2_ras 2 19 1m_ben Ip2_Cas 3 lS nu18 Im_sl1 4 17 nu17 Ip2_parvt 5 lS Im_parrd nu6 6 15 Ix_pveO nu7 7 14 Ix_pvel nuS 8 13 1m_act nu9 9 12 Ix_ve gnd 10 11 null ...

Page 370: ... _ l 1 _ r f _ r 2 i 7 s of _ T I 7J f 1 _ _ I I I l J41 1 _ 1 _ I _ _ f i _ S L E SU 0 J L f i L _ _ 4SB _ j f _ I b_SC R _ I 4 L e P R Y L 1 i K r s4 L xL I I 7 t f I I I i f _ f I fI L 1 l _ ...

Page 371: ...r I I I I E L J l1Ll j f J l a I f i t 1 7t r i L L l 1 r J t I 3 N l I J 1 f I t _ __ _ _ _ _ _ _ _ t _ ...

Page 372: ......

Page 373: ......

Page 374: ...6 Bit Data 16 Bit Address FFFFOOOO FFFEFFFF FFOOOOOO 24 Bit Addresses FFFEFFFF FFFFOOOO FFOOOOOO 32 Bit Data 16 Bit Data 24 Bit Addresses 00000000 00000000 FEFFFFFF 32 Bit Addresses FFOOOOOO FEFFFFFF FFOOOOOO 32 Bit Data 32 Bit Addresses 16 Bit Data I O Type 2 RAM Video FFFFFFFF V11E 16 Bit Data 00000000 FFFFFFFF 00000000 FFFFFFFF FFFFFFFF Type 3 VME 32 Bit Data Type 1 Type 2 ...

Page 375: ... IEbus Slave Address 1 fapping I ...

Page 376: ...I _ _ I I l t I _ _ _ It I I I _ _ _ _L _ r r T _ I i 1 I t _ _ t r 1 _ t _ _ __ _ _ _ _ _6 _ _ r _ 4 _ _ 1 I ___ 1 __ __ I j 1 I I l f 1 i t _ I I I I T _ I t _ _ l _ _ _L __ _ I _ _ _ _ _ I j o _ _ _ _ __ 0 1 i _ l r _ __ _ l I I i1 T I i 1 r i I I _ nl i I I t I I I I L r _ _ _ _l _ _ _ _ _ __ I i I r _ _ _ _ I _4 __ __ __ __ __ _ t t I_4 1 i t1 T r ...

Page 377: ..._ _ _ __ _ J 1 _ _L_ I t _ l_ _ __ _ _ __ _ _ _ _ _ _ i l l 1 _ I I f I r I I I r _ _ _ _ _ _ I i _ l t v aJ 0 C lv a I l b J J r i __ _ L 0 x BJ t LG k N c J35 _ T r t N DLW _ V _ O t Ou lj WOjJ ttt L c X H LE I i h _ v C R S s _ ...

Page 378: ... f _ t I 1 t f t T 4 r j j j _ 1 i JJ A Oj Ex ___ I I I i I I I i I I 1 1 1 I 4 1 5TM LwE I J i 11 t fA I JL 1 I j I ii i J I I l r _ A J I __ l __1 r____ _ L 0 t I I _ I _ _ t I I I r I j I 1 f r 4 4 I to I ...

Page 379: ...mmu_vme b_55el pl_bbsy C b_sbbin b_aen b_oecpu b_ssoe b_as b_uds b_lds pl_dtack b_dt ack b_acken q ...

Page 380: ... ...

Page 381: ...I mmu vmo P l_bbs L l _ l _ b_sbbin 1 1 4 b_ooq _u _ __ _ _I b_aen _ b_ 5500_ _ 1 _ ...

Page 382: ... V 1 fj un r su o J f i u b_lds ck k n 4 c 60 iJu II lLJII p_8S G D b_rer p_ber p_hal O pl_bb b_en l J b_ 0f a _ _ b_torrn b_freeze I Cur 11_ _ r I ...

Page 383: ...I r c_60 p2_as pc_ type 1 b_ssel pl_bbs b_sbb i n J b_aen b_oeq u b ssoe b_as b_uds lds pt _d tack b dlack b acken 1 b_sbr b hqoul 1 1 I ...

Page 384: ... r 7 U U L u ULfl pt_br3 pl_bbsy pl_dfack s_dma x_dmaen r I UME_Oev ice Jkqu i r s_ url 1 J an dJ lcco5ses _r2 _fJus I _ ...

Page 385: ... L f r f I I 1 I _ _ _ _ _ r c_60 pl_bbsy s_ack p2_as x_dmaen pl_dfack pl_as pl_sas b_Ssxdma xreq b_Iock s_xreq p_back r p_br p_bg pl_ds0 pl dst 9 pI ds J b_ do ...

Page 386: ... _ _ _ _ Il _ c 60 pl_bbs s_8ck p_as x_dmaen pl_dtack _1 pl_as pl_sas b_5sxdma s_xreq b_lock p_back p_br p_bg s_dma n n I ...

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Page 404: ...c A 1 IS qf M TT lr II Ih t t r If T S IllS ltre Mm io f JilltJ I I ulrl lilt SC C _ca ck Iq Ii leo M T E _ l __ _ _ _ _ tlbf 1113 J l 6 1 1 0 1 1 I ft lb J 4 l i 1 I 1 2r 11M lI 13 13 10 _cA l OJ I 30 I F UI 3 l al vl LtD p2 d 11 211 7 iOy X X t X lIq O lAUD m tS4c k h CI I lfo Ino I h07 Ip 9 ttlwQl 1 1 If Inr 1 1 r rr r ttlrde rtJ 111 1 If II rl 3lS hrhr CItt 11 c ro I lUll 1m l uo IIJoS I ftl p...

Page 405: ...Hardware Engineering Manual I II 1 of20 October 1986 Changed revision number to comply with Doc Control s new numbering scheme 1 12 20 January 1987 Corrected revision level to reflect new numbering scheme This is the only change in the manual 1 13 10 May 1987 Added changes from the latest ECD PALs 210 202 408 25 MHz clock removed TOO circuit revised U P ...